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Date: Thu, 30 Aug 2018 22:43:55 +0300 From: Dmitry Osipenko <digetx@...il.com> To: Thierry Reding <thierry.reding@...il.com>, Jonathan Hunter <jonathanh@...dia.com>, Peter De Schrijver <pdeschrijver@...dia.com>, "Rafael J. Wysocki" <rjw@...ysocki.net>, Viresh Kumar <viresh.kumar@...aro.org>, Rob Herring <robh+dt@...nel.org> Cc: linux-pm@...r.kernel.org, devicetree@...r.kernel.org, linux-tegra@...r.kernel.org, linux-kernel@...r.kernel.org Subject: [PATCH v1 4/5] ARM: dts: tegra20: Add CPU Operating Performance Points Add CPU's Operating Performance Points to the device tree, they are used by the CPUFreq driver and allow to setup thermal throttling for the boards by linking the cooling device (CPU) with thermal sensors via thermal-zones description. Signed-off-by: Dmitry Osipenko <digetx@...il.com> --- arch/arm/boot/dts/tegra20.dtsi | 58 ++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 01398db0c9c7..4415de0f7c65 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -859,6 +859,52 @@ status = "disabled"; }; + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp@...000000 { + clock-latency-ns = <2000>; + opp-hz = /bits/ 64 <216000000>; + opp-suspend; + }; + + opp@...000000 { + clock-latency-ns = <125000>; + opp-hz = /bits/ 64 <312000000>; + }; + + opp@...000000 { + clock-latency-ns = <125000>; + opp-hz = /bits/ 64 <456000000>; + }; + + opp@...000000 { + clock-latency-ns = <125000>; + opp-hz = /bits/ 64 <608000000>; + }; + + opp@...000000 { + clock-latency-ns = <125000>; + opp-hz = /bits/ 64 <760000000>; + }; + + opp@...000000 { + clock-latency-ns = <125000>; + opp-hz = /bits/ 64 <816000000>; + }; + + opp@...000000 { + clock-latency-ns = <125000>; + opp-hz = /bits/ 64 <912000000>; + }; + + opp@...0000000 { + clock-latency-ns = <125000>; + opp-hz = /bits/ 64 <1000000000>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -867,12 +913,24 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + clocks = <&tegra_car TEGRA20_CLK_PLL_X>, + <&tegra_car TEGRA20_CLK_PLL_P>, + <&tegra_car TEGRA20_CLK_CCLK>; + clock-names = "pll_x", "backup", "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + clocks = <&tegra_car TEGRA20_CLK_PLL_X>, + <&tegra_car TEGRA20_CLK_PLL_P>, + <&tegra_car TEGRA20_CLK_CCLK>; + clock-names = "pll_x", "backup", "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; }; -- 2.18.0
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