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Date:   Tue, 28 Aug 2018 08:13:45 +1000
From:   Benjamin Herrenschmidt <>
To:     Nicholas Piggin <>
Cc:     Peter Zijlstra <>,
        Will Deacon <>,
        Linus Torvalds <>,
        Andrew Lutomirski <>,
        the arch/x86 maintainers <>,
        Borislav Petkov <>,
        Rik van Riel <>,
        Jann Horn <>,
        Adin Scannell <>,
        Dave Hansen <>,
        Linux Kernel Mailing List <>,
        linux-mm <>,
        David Miller <>,
        Martin Schwidefsky <>,
        Michael Ellerman <>
Subject: Re: [PATCH 3/4] mm/tlb, x86/mm: Support invalidating TLB caches for

On Mon, 2018-08-27 at 19:02 +1000, Nicholas Piggin wrote:
> > More tlbies ? With the cost of the broadasts on the fabric ? I don't
> > think so.. or I'm not understanding your point...
> More tlbies are no good, but there will be some places where it works
> out much better (and fewer tlbies). Worst possible case for current code
> is a big unmap with lots of scattered page sizes. We _should_ get that
> with just a single PID flush at the end, but what we will get today is
> a bunch of PID and VA flushes.
> I don't propose doing that though, I'd rather be explicit about
> tracking start and end range of each page size. Still not "optimal"
> but neither is existing single range for sparse mappings... anyway it
> will need to be profiled, but my point is we don't really fit exactly
> what x86/arm want.

If we have an arch specific part, we could just remember up to N
"large" pages there without actually flushing, and if that overflows,
upgrade to a full flush.


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