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Message-ID: <20180831125451.GK2283@lahna.fi.intel.com>
Date: Fri, 31 Aug 2018 15:54:51 +0300
From: Mika Westerberg <mika.westerberg@...ux.intel.com>
To: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
Cc: Lee Jones <lee.jones@...aro.org>,
Hans de Goede <hdegoede@...hat.com>,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v1 4/7] mfd: intel_soc_pmic_bxtwc: Chain power button
IRQs as well
On Thu, Aug 30, 2018 at 07:52:52PM +0300, Andy Shevchenko wrote:
> Power button IRQ actually has a second level of interrupts to
> distinguish between UI and POWER buttons. Moreover, current
> implementation looks awkward in approach to handle second level IRQs by
> first level related IRQ chip.
>
> To address above issues, split power button IRQ to be chained as well.
>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@...ux.intel.com>
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