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Message-ID: <CA+sq2Cc_fdTjSJx1BdietRThfK=gn3Sy__=K4iQNQDCBTa+JyA@mail.gmail.com>
Date: Sat, 1 Sep 2018 00:05:10 +0530
From: Sunil Kovvuri <sunil.kovvuri@...il.com>
To: Arnd Bergmann <arnd@...db.de>
Cc: LKML <linux-kernel@...r.kernel.org>, olof@...om.net,
LAKML <linux-arm-kernel@...ts.infradead.org>,
linux-soc@...r.kernel.org, Sunil Goutham <sgoutham@...vell.com>
Subject: Re: [PATCH 11/15] soc: octeontx2: Add Marvell OcteonTX2 CGX driver
On Fri, Aug 31, 2018 at 11:59 PM Arnd Bergmann <arnd@...db.de> wrote:
>
> On Fri, Aug 31, 2018 at 6:01 PM Sunil Kovvuri <sunil.kovvuri@...il.com> wrote:
> > On Fri, Aug 31, 2018 at 7:50 PM Arnd Bergmann <arnd@...db.de> wrote:
>
> >
> > Thanks for the suggestion, that does makes sense.
> > Actually i did thought about it, but i was skeptical if it would be
> > acceptable to make
> > a single module out of drivers registering for two different PCI devices.
>
> I don't think it matters much whether there is one module or two
> (others might have a strong opinion one way or the other).
>
> What is important though are these two points:
>
> - How to represent the two PCI devices to user space: You should only
> have one interface to user space I think, and this should be similar
> to how other drivers manage similar cases (I don't actually know what they
> do, but I assume you've done some research here)
>
> - How you connect find the pair of devices: Generally speaking while
> the SoC might only have one of each, you shouldn't make that assumption
> in the code, but instead have a reliable way of having one driver wait
> for the other driver to finish probing so you can match the pair.
>
Agreed.
I do have a patch in works for that, i.e to defer AF driver probe till
CGX driver is loaded.
https://github.com/sunilkovvuri/rvu_drivers/commit/27b449087c16224a9e93dd91d6d9f734b5210bed
> > Will wait for few more days for more feedback from anyone and port v2 series.
>
> Ok.
>
> Arnd
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