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Message-ID: <20180902064601.183036-129-alexander.levin@microsoft.com>
Date:   Sun, 2 Sep 2018 13:05:45 +0000
From:   Sasha Levin <Alexander.Levin@...rosoft.com>
To:     "stable@...r.kernel.org" <stable@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
CC:     Quentin Schulz <quentin.schulz@...tlin.com>,
        Paul Burton <paul.burton@...s.com>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "mark.rutland@....com" <mark.rutland@....com>,
        "ralf@...ux-mips.org" <ralf@...ux-mips.org>,
        "jhogan@...nel.org" <jhogan@...nel.org>,
        "linux-mips@...ux-mips.org" <linux-mips@...ux-mips.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "thomas.petazzoni@...tlin.com" <thomas.petazzoni@...tlin.com>,
        Sasha Levin <Alexander.Levin@...rosoft.com>
Subject: [PATCH AUTOSEL 4.18 129/131] MIPS: mscc: ocelot: fix length of memory
 address space for MIIM

From: Quentin Schulz <quentin.schulz@...tlin.com>

[ Upstream commit 49e5bb13adc11fe6e2e40f65c04f3a461aea1fec ]

The length of memory address space for MIIM0 is from 0x7107009c to
0x710700bf included which is 36 bytes long in decimal, or 0x24 bytes in
hexadecimal and not 0x36.

Fixes: 49b031690abe ("MIPS: mscc: Add switch to ocelot")

Signed-off-by: Quentin Schulz <quentin.schulz@...tlin.com>
Acked-by: Alexandre Belloni <alexandre.belloni@...tlin.com>
Signed-off-by: Paul Burton <paul.burton@...s.com>
Patchwork: https://patchwork.linux-mips.org/patch/20013/
Cc: robh+dt@...nel.org
Cc: mark.rutland@....com
Cc: ralf@...ux-mips.org
Cc: jhogan@...nel.org
Cc: linux-mips@...ux-mips.org
Cc: devicetree@...r.kernel.org
Cc: linux-kernel@...r.kernel.org
Cc: thomas.petazzoni@...tlin.com
Signed-off-by: Sasha Levin <alexander.levin@...rosoft.com>
---
 arch/mips/boot/dts/mscc/ocelot.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi
index 4f33dbc67348..7096915f26e0 100644
--- a/arch/mips/boot/dts/mscc/ocelot.dtsi
+++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
@@ -184,7 +184,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "mscc,ocelot-miim";
-			reg = <0x107009c 0x36>, <0x10700f0 0x8>;
+			reg = <0x107009c 0x24>, <0x10700f0 0x8>;
 			interrupts = <14>;
 			status = "disabled";
 
-- 
2.17.1

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