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Message-ID: <CAGb2v64Y0ui6ZvAJqc2dXMKtSSQJ-T4ubrV9188JTV7aFSrFCA@mail.gmail.com>
Date: Tue, 4 Sep 2018 17:18:47 +0800
From: Chen-Yu Tsai <wens@...e.org>
To: Jernej Skrabec <jernej.skrabec@...l.net>
Cc: Rob Herring <robh+dt@...nel.org>,
Maxime Ripard <maxime.ripard@...tlin.com>,
Mark Rutland <mark.rutland@....com>,
Mike Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
David Airlie <airlied@...ux.ie>,
Archit Taneja <architt@...eaurora.org>,
Andrzej Hajda <a.hajda@...sung.com>,
devicetree <devicetree@...r.kernel.org>,
linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
linux-kernel <linux-kernel@...r.kernel.org>,
linux-clk <linux-clk@...r.kernel.org>,
dri-devel <dri-devel@...ts.freedesktop.org>,
linux-sunxi <linux-sunxi@...glegroups.com>
Subject: Re: [PATCH 05/27] clk: sunxi-ng: Use u64 for calculation of NM rate
On Sun, Sep 2, 2018 at 3:27 PM Jernej Skrabec <jernej.skrabec@...l.net> wrote:
>
> Allwinner H6 SoC has multiplier N range between 1 and 254. Since parent
> rate is 24MHz, intermediate result when calculating final rate easily
> overflows 32 bit variable.
>
> Because of that, introduce function for calculating clock rate which
> uses 64 bit variable for intermediate result.
>
> Signed-off-by: Jernej Skrabec <jernej.skrabec@...l.net>
The code looks good. The A80's Video PLLs are also affected by this.
The range for N on the A80 is 12 ~ 255.
Can you add fixes and stable tags?
ChenYu
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