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Message-Id: <1536103345-1919-5-git-send-email-vnkgutta@codeaurora.org>
Date: Tue, 4 Sep 2018 16:22:25 -0700
From: Venkata Narendra Kumar Gutta <vnkgutta@...eaurora.org>
To: Borislav Petkov <bp@...en8.de>, evgreen@...omium.org,
robh@...nel.org, mchehab@...nel.org, linux-edac@...r.kernel.org,
linux-kernel@...r.kernel.org, Andy Gross <andy.gross@...aro.org>,
David Brown <david.brown@...aro.org>,
linux-arm-msm@...r.kernel.org, linux-soc@...r.kernel.org,
robh+dt@...nel.org, mark.rutland@....com,
devicetree@...r.kernel.org, tsoni@...eaurora.org,
ckadabi@...eaurora.org, rishabhb@...eaurora.org,
swboyd@...omium.org, bjorn.andersson@...aro.org
Cc: Venkata Narendra Kumar Gutta <vnkgutta@...eaurora.org>
Subject: [PATCH v4 4/4] dt-bindings: msm: Update documentation of qcom,llcc
Add reg-names and interrupts for LLCC documentation and the usage
examples. llcc broadcast base is added in addition to llcc base,
which is used for llcc broadcast writes.
Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@...eaurora.org>
Reviewed-by: Rob Herring <robh@...nel.org>
---
.../devicetree/bindings/arm/msm/qcom,llcc.txt | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
index 5e85749..2e007dc 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
@@ -16,11 +16,26 @@ Properties:
- reg:
Usage: required
Value Type: <prop-encoded-array>
- Definition: Start address and the the size of the register region.
+ Definition: The first element specifies the llcc base start address and
+ the size of the register region. The second element specifies
+ the llcc broadcast base address and size of the register region.
+
+- reg-names:
+ Usage: required
+ Value Type: <stringlist>
+ Definition: Register region names. Must be "llcc_base", "llcc_bcast_base".
+
+- interrupts:
+ Usage: required
+ Definition: The interrupt is associated with the llcc edac device.
+ It's used for llcc cache single and double bit error detection
+ and reporting.
Example:
cache-controller@...0000 {
compatible = "qcom,sdm845-llcc";
- reg = <0x1100000 0x250000>;
+ reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
+ reg-names = "llcc_base", "llcc_bcast_base";
+ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
--
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