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Date:   Thu, 6 Sep 2018 16:31:16 +0200
From:   Arnd Bergmann <arnd@...db.de>
To:     Guo Ren <ren_guo@...ky.com>
Cc:     linux-arch <linux-arch@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Daniel Lezcano <daniel.lezcano@...aro.org>,
        Jason Cooper <jason@...edaemon.net>,
        c-sky_gcc_upstream@...ky.com, gnu-csky@...tor.com,
        Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
        wbx@...ibc-ng.org, Greentime Hu <green.hu@...il.com>
Subject: Re: [PATCH V3 06/26] csky: Cache and TLB routines

On Wed, Sep 5, 2018 at 2:08 PM Guo Ren <ren_guo@...ky.com> wrote:

> diff --git a/arch/csky/include/asm/io.h b/arch/csky/include/asm/io.h
> new file mode 100644
> index 0000000..fcb2142
> --- /dev/null
> +++ b/arch/csky/include/asm/io.h
> @@ -0,0 +1,23 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
> +#ifndef __ASM_CSKY_IO_H
> +#define __ASM_CSKY_IO_H
> +
> +#include <abi/pgtable-bits.h>
> +#include <linux/types.h>
> +#include <linux/version.h>
> +
> +extern void __iomem *ioremap(phys_addr_t offset, size_t size);
> +
> +extern void iounmap(void *addr);
> +
> +extern int remap_area_pages(unsigned long address, phys_addr_t phys_addr,
> +               size_t size, unsigned long flags);
> +
> +#define ioremap_nocache(phy, sz)       ioremap(phy, sz)
> +#define ioremap_wc ioremap_nocache
> +#define ioremap_wt ioremap_nocache
> +
> +#include <asm-generic/io.h>

It is very unusual for an architecture to not need special handling in asm/io.h,
to do the proper barriers etc.

Can you describe how C-Sky hardware implements MMIO?

In particular:

- Is a read from uncached memory always serialized with DMA, and with
  other CPUs doing MMIO access to a different address?

- How does endianess work? Are there any buses that flip bytes around
  when running big-endian, or do you always do that in software?

        Arnd

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