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Message-ID: <20180910112709.GH12979@infradead.org>
Date: Mon, 10 Sep 2018 04:27:09 -0700
From: Christoph Hellwig <hch@...radead.org>
To: Atish Patra <atish.patra@....com>
Cc: palmer@...ive.com, linux-riscv@...ts.infradead.org,
hch@...radead.org, anup@...infault.org, mark.rutland@....com,
Damien.LeMoal@....com, jason@...edaemon.net,
ard.biesheuvel@...aro.org, marc.zyngier@....com,
gregkh@...uxfoundation.org, dmitriy@...-tech.org,
linux-kernel@...r.kernel.org, jeremy.linton@....com,
catalin.marinas@....com, tglx@...utronix.de
Subject: Re: [PATCH v3 09/12] RISC-V: User WRITE_ONCE instead of direct access
On Thu, Sep 06, 2018 at 01:05:32AM -0700, Atish Patra wrote:
> The secondary harts spin on couple of per cpu variables until both of
> these are non-zero so it's not necessary to have any ordering here.
> However, WRITE_ONCE should be used to avoid tearing.
We normally pair WRITE_ONCE with READ_ONCE. But it seems like the
reader side is in assembly code, so this should be ok:
Reviewed-by: Christoph Hellwig <hch@....de>
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