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Message-ID: <nycvar.YFH.7.76.1809101343370.15880@cbobk.fhfr.pm>
Date:   Mon, 10 Sep 2018 13:46:16 +0200 (CEST)
From:   Jiri Kosina <jikos@...nel.org>
To:     Thomas Gleixner <tglx@...utronix.de>
cc:     Ingo Molnar <mingo@...hat.com>,
        Peter Zijlstra <peterz@...radead.org>,
        Josh Poimboeuf <jpoimboe@...hat.com>,
        Andrea Arcangeli <aarcange@...hat.com>,
        "Woodhouse, David" <dwmw@...zon.co.uk>,
        Andi Kleen <ak@...ux.intel.com>,
        Tim Chen <tim.c.chen@...ux.intel.com>,
        "Schaufler, Casey" <casey.schaufler@...el.com>,
        linux-kernel@...r.kernel.org, x86@...nel.org
Subject: Re: [PATCH v5 2/2] x86/speculation: Enable cross-hyperthread spectre
 v2 STIBP mitigation

On Mon, 10 Sep 2018, Jiri Kosina wrote:

> > That looks much more palatable. One missing piece is the sysfs 
> > mitigation file for spectre v2. That should reflect STIPB state as well.
> 
> FWIW, we're missing a bit more in that area, namely RSB stuffing on 
> context switch, IBRS (even through only around fw) and IBPB; those are 
> only signalled in dmesg during bootup.

Nah, IBPB is actuall there, sorry. So I'll add reporting of STIBP + fixup 
the missing reporting of RSB_CTXSW for v6.

-- 
Jiri Kosina
SUSE Labs

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