linux-kernel - Re: [stable PATCH 2/2] arm64: Handle mismatched cache type

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Message-ID: <20180912193834.GG21563@kroah.com>
Date:   Wed, 12 Sep 2018 21:38:34 +0200
From:   Greg KH <gregkh@...uxfoundation.org>
To:     Suzuki K Poulose <suzuki.poulose@....com>
Cc:     stable@...r.kernel.org, will.deacon@....com, mark.rutland@....com,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        catalin.marinas@....com
Subject: Re: [stable PATCH 2/2] arm64: Handle mismatched cache type

On Tue, Sep 04, 2018 at 10:10:10AM +0100, Suzuki K Poulose wrote:
> commit 314d53d297980676011e6fd83dac60db4a01dc70 upstream
> 
> Track mismatches in the cache type register (CTR_EL0), other
> than the D/I min line sizes and trap user accesses if there are any.
> 
> Fixes: be68a8aaf925 ("arm64: cpufeature: Fix CTR_EL0 field definitions")
> Cc: <stable@...r.kernel.org> # v4.9

Same 4.9 question here as well.

thanks,

greg k-h