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Message-ID: <20180919091524.rgbk4m6ht34idkpd@verge.net.au>
Date: Wed, 19 Sep 2018 11:15:24 +0200
From: Simon Horman <horms@...ge.net.au>
To: Phil Edworthy <phil.edworthy@...esas.com>
Cc: Geert Uytterhoeven <geert@...ux-m68k.org>,
Laurent Pinchart <laurent.pinchart@...asonboard.com>,
Jacopo Mondi <jacopo@...ndi.org>,
Linus Walleij <linus.walleij@...aro.org>,
linux-gpio@...r.kernel.org, linux-renesas-soc@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 3/3] ARM: dts: r9a06g032: Add pinctrl node
On Mon, Sep 17, 2018 at 05:36:09PM +0100, Phil Edworthy wrote:
> This provides a pinctrl driver for the Renesas R9A06G032 SoC
>
> Based on a patch originally written by Michel Pollet at Renesas.
>
> Signed-off-by: Phil Edworthy <phil.edworthy@...esas.com>
Thanks Phil, I will defer this patch pending acceptance of the bindings.
Please continue to repost this patch with updates to the bindings
or otherwise ping me once they have been accepted.
> ---
> v3:
> - No changes.
> v2:
> - Add "renesas,rzn1-pinctrl" compatible fallback string
> - Register size corrected.
> ---
> arch/arm/boot/dts/r9a06g032.dtsi | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
> index eaf94976ed6d..2322268bc862 100644
> --- a/arch/arm/boot/dts/r9a06g032.dtsi
> +++ b/arch/arm/boot/dts/r9a06g032.dtsi
> @@ -165,6 +165,14 @@
> status = "disabled";
> };
>
> + pinctrl: pin-controller@...67000 {
> + compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
> + reg = <0x40067000 0x1000>, <0x51000000 0x480>;
> + clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
> + clock-names = "bus";
> + status = "okay";
> + };
> +
> gic: gic@...01000 {
> compatible = "arm,cortex-a7-gic", "arm,gic-400";
> interrupt-controller;
> --
> 2.17.1
>
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