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Message-ID: <201809190813.xn0x079o%fengguang.wu@intel.com>
Date: Wed, 19 Sep 2018 08:41:31 +0800
From: kbuild test robot <lkp@...el.com>
To: Dilip Kota <dkota@...eaurora.org>
Cc: kbuild-all@...org, swboyd@...omium.org, dianders@...omium.org,
broonie@...nel.org, mka@...omium.org, linux-kernel@...r.kernel.org,
linux-spi@...r.kernel.org, linux-arm-msm@...r.kernel.org,
Girish Mahadevan <girishm@...eaurora.org>,
Dilip Kota <dkota@...eaurora.org>
Subject: Re: [PATCH V4 3/4] spi: spi-geni-qcom: Add SPI driver support for
GENI based QUP
Hi Girish,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on spi/for-next]
[also build test ERROR on v4.19-rc4 next-20180918]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Dilip-Kota/spi-geni-qcom-QUP-SPI-GENI-driver-and-SPI-device-tree-bindings/20180919-043055
base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
config: xtensa-allyesconfig (attached as .config)
compiler: xtensa-linux-gcc (GCC) 8.1.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=8.1.0 make.cross ARCH=xtensa
All errors (new ones prefixed by >>):
drivers/spi/spi-geni-qcom.c: In function 'spi_geni_init':
>> drivers/spi/spi-geni-qcom.c:236:10: error: implicit declaration of function 'GENI_SE_VERSION_MAJOR'; did you mean 'XCHAL_HW_VERSION_MAJOR'? [-Werror=implicit-function-declaration]
major = GENI_SE_VERSION_MAJOR(ver);
^~~~~~~~~~~~~~~~~~~~~
XCHAL_HW_VERSION_MAJOR
>> drivers/spi/spi-geni-qcom.c:237:10: error: implicit declaration of function 'GENI_SE_VERSION_MINOR'; did you mean 'XCHAL_HW_VERSION_MINOR'? [-Werror=implicit-function-declaration]
minor = GENI_SE_VERSION_MINOR(ver);
^~~~~~~~~~~~~~~~~~~~~
XCHAL_HW_VERSION_MINOR
cc1: some warnings being treated as errors
vim +236 drivers/spi/spi-geni-qcom.c
208
209 static int spi_geni_init(struct spi_geni_master *mas)
210 {
211 struct geni_se *se = &mas->se;
212 unsigned int proto, major, minor, ver;
213
214 pm_runtime_get_sync(mas->dev);
215
216 proto = geni_se_read_proto(se);
217 if (proto != GENI_SE_SPI) {
218 dev_err(mas->dev, "Invalid proto %d\n", proto);
219 pm_runtime_put(mas->dev);
220 return -ENXIO;
221 }
222 mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se);
223 mas->rx_fifo_depth = geni_se_get_rx_fifo_depth(se);
224
225 /* Width of Tx and Rx FIFO is same */
226 mas->fifo_width_bits = geni_se_get_tx_fifo_width(se);
227
228 /*
229 * Hardware programming guide suggests to configure
230 * RX FIFO RFR level to fifo_depth-2.
231 */
232 geni_se_init(se, 0x0, mas->tx_fifo_depth - 2);
233 /* Transmit an entire FIFO worth of data per IRQ */
234 mas->tx_wm = 1;
235 ver = geni_se_get_qup_hw_version(se);
> 236 major = GENI_SE_VERSION_MAJOR(ver);
> 237 minor = GENI_SE_VERSION_MINOR(ver);
238
239 if (major == 1 && minor == 0)
240 mas->oversampling = 2;
241 else
242 mas->oversampling = 1;
243
244 pm_runtime_put(mas->dev);
245 return 0;
246 }
247
---
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