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Date: Thu, 20 Sep 2018 02:48:06 +0000 From: Sasha Levin <Alexander.Levin@...rosoft.com> To: "stable@...r.kernel.org" <stable@...r.kernel.org>, "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org> CC: Akshu Agrawal <akshu.agrawal@....com>, Stephen Boyd <sboyd@...nel.org>, Sasha Levin <Alexander.Levin@...rosoft.com> Subject: [PATCH AUTOSEL 4.18 55/56] clk: x86: Set default parent to 48Mhz From: Akshu Agrawal <akshu.agrawal@....com> [ Upstream commit bded6c03e398dc6e862dc8301fb9a60175740653 ] System clk provided in ST soc can be set to: 48Mhz, non-spread 25Mhz, spread To get accurate rate, we need it to set it at non-spread option which is 48Mhz. Signed-off-by: Akshu Agrawal <akshu.agrawal@....com> Reviewed-by: Daniel Kurtz <djkurtz@...omium.org> Fixes: 421bf6a1f061 ("clk: x86: Add ST oscout platform clock") Signed-off-by: Stephen Boyd <sboyd@...nel.org> Signed-off-by: Sasha Levin <alexander.levin@...rosoft.com> --- drivers/clk/x86/clk-st.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/x86/clk-st.c b/drivers/clk/x86/clk-st.c index fb62f3938008..3a0996f2d556 100644 --- a/drivers/clk/x86/clk-st.c +++ b/drivers/clk/x86/clk-st.c @@ -46,7 +46,7 @@ static int st_clk_probe(struct platform_device *pdev) clk_oscout1_parents, ARRAY_SIZE(clk_oscout1_parents), 0, st_data->base + CLKDRVSTR2, OSCOUT1CLK25MHZ, 3, 0, NULL); - clk_set_parent(hws[ST_CLK_MUX]->clk, hws[ST_CLK_25M]->clk); + clk_set_parent(hws[ST_CLK_MUX]->clk, hws[ST_CLK_48M]->clk); hws[ST_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1", "oscout1_mux", 0, st_data->base + MISCCLKCNTL1, OSCCLKENB, -- 2.17.1
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