lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20180920095727.11868-2-weiyi.lu@mediatek.com>
Date:   Thu, 20 Sep 2018 17:57:24 +0800
From:   Weiyi Lu <weiyi.lu@...iatek.com>
To:     Matthias Brugger <matthias.bgg@...il.com>,
        Stephen Boyd <sboyd@...eaurora.org>,
        Rob Herring <robh@...nel.org>
CC:     James Liao <jamesjj.liao@...iatek.com>,
        Fan Chen <fan.chen@...iatek.com>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>,
        <linux-mediatek@...ts.infradead.org>, <linux-clk@...r.kernel.org>,
        <srv_heupstream@...iatek.com>, Weiyi Lu <weiyi.lu@...iatek.com>
Subject: [PATCH v1 0/3] update Mediatek MT2712 clock

This series is based on v4.19-rc1.
Basically, it's for the 3rd ECO design change of MT2712.
And also add support for switching pll reference source
for some MT2712 projects.

*** BLURB HERE ***

Weiyi Lu (3):
  dt-bindings: clock: add clock for MT2712
  clk: mediatek: update clock driver of MT2712
  clk: mediatek: mt2712: add pll reference support

 drivers/clk/mediatek/clk-mt2712.c      | 95 ++++++++++++++++++++++++++--------
 include/dt-bindings/clock/mt2712-clk.h |  3 +-
 2 files changed, 76 insertions(+), 22 deletions(-)

-- 
2.12.5.2.gbdf23ab

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ