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Message-ID: <b7cadb6f-d17f-3be7-38f4-1104026ea745@st.com>
Date:   Thu, 20 Sep 2018 14:53:38 +0200
From:   Alexandre Torgue <alexandre.torgue@...com>
To:     Amelie Delaunay <amelie.delaunay@...com>,
        Maxime Coquelin <mcoquelin.stm32@...il.com>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>
CC:     <linux-stm32@...md-mailman.stormreply.com>,
        <linux-arm-kernel@...ts.infradead.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] ARM: dts: stm32: update rtc st,syscfg property on
 stm32h743

Hi Amélie

On 08/22/2018 11:45 AM, Amelie Delaunay wrote:
> To fit with latest rtc driver updates, rtc st,syscfg property must contain
> the control register offset of pwrcfg and the mask corresponding to the
> DBP (Disable Backup Protection) bit.
> 
> Signed-off-by: Amelie Delaunay <amelie.delaunay@...com>
> ---
>   arch/arm/boot/dts/stm32h743.dtsi | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi
> index 637beff..cbdd69c 100644
> --- a/arch/arm/boot/dts/stm32h743.dtsi
> +++ b/arch/arm/boot/dts/stm32h743.dtsi
> @@ -472,7 +472,7 @@
>   			interrupt-parent = <&exti>;
>   			interrupts = <17 IRQ_TYPE_EDGE_RISING>;
>   			interrupt-names = "alarm";
> -			st,syscfg = <&pwrcfg>;
> +			st,syscfg = <&pwrcfg 0x00 0x100>;
>   			status = "disabled";
>   		};
>   
> 

Applied on stm32-next.

Thanks.
Alex

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