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Message-ID: <1537952920.14753.6.camel@mhfsdcap03>
Date: Wed, 26 Sep 2018 17:08:40 +0800
From: Honghui Zhang <honghui.zhang@...iatek.com>
To: Lorenzo Pieralisi <lorenzo.pieralisi@....com>
CC: <marc.zyngier@....com>, <bhelgaas@...gle.com>,
<matthias.bgg@...il.com>, <linux-arm-kernel@...ts.infradead.org>,
<linux-mediatek@...ts.infradead.org>, <linux-pci@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
<yingjoe.chen@...iatek.com>, <eddie.huang@...iatek.com>,
<ryder.lee@...iatek.com>, <ulf.hansson@...aro.org>,
<hongkun.cao@...iatek.com>, <youlin.pei@...iatek.com>,
<yong.wu@...iatek.com>, <yt.shen@...iatek.com>,
<sean.wang@...iatek.com>, <xinping.qian@...iatek.com>
Subject: Re: [PATCH v4 2/4] PCI: mediatek: enable msi after clock enabled
On Fri, 2018-09-21 at 17:46 +0100, Lorenzo Pieralisi wrote:
> On Mon, Sep 10, 2018 at 05:50:21PM +0800, honghui.zhang@...iatek.com wrote:
> > From: Honghui Zhang <honghui.zhang@...iatek.com>
> >
> > The clocks was not enabled when enable MSI. This patch fix this
> > issue by calling mtk_pcie_enable_msi in mtk_pcie_startup_port_v2
> > since the clock was all enabled at that time.
> >
> > The function of mtk_pcie_startup_port_v2's define location is
> > re-arranged to avoid mtk_pcie_enable_msi's forward declaration.
> >
> > Signed-off-by: Honghui Zhang <honghui.zhang@...iatek.com>
> > Reviewed-by: Ryder Lee <ryder.lee@...iatek.com>
> > ---
> > drivers/pci/controller/pcie-mediatek.c | 143 +++++++++++++++++----------------
> > 1 file changed, 72 insertions(+), 71 deletions(-)
>
> Can you read:
>
> https://marc.info/?l=linux-pci&m=150905742808166&w=2
>
> follow it and adapt this patch and the others accordingly please ?
>
Sorry, I mixed those patches together. I will split a new patch to do
the code re-arrangement to avoid forward declaration.
Thanks.
> Thanks,
> Lorenzo
>
> > diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
> > index 20b9088..5aba43a 100644
> > --- a/drivers/pci/controller/pcie-mediatek.c
> > +++ b/drivers/pci/controller/pcie-mediatek.c
> > @@ -398,75 +398,6 @@ static struct pci_ops mtk_pcie_ops_v2 = {
> > .write = mtk_pcie_config_write,
> > };
> >
> > -static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
> > -{
> > - struct mtk_pcie *pcie = port->pcie;
> > - struct resource *mem = &pcie->mem;
> > - const struct mtk_pcie_soc *soc = port->pcie->soc;
> > - u32 val;
> > - size_t size;
> > - int err;
> > -
> > - /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
> > - if (pcie->base) {
> > - val = readl(pcie->base + PCIE_SYS_CFG_V2);
> > - val |= PCIE_CSR_LTSSM_EN(port->slot) |
> > - PCIE_CSR_ASPM_L1_EN(port->slot);
> > - writel(val, pcie->base + PCIE_SYS_CFG_V2);
> > - }
> > -
> > - /* Assert all reset signals */
> > - writel(0, port->base + PCIE_RST_CTRL);
> > -
> > - /*
> > - * Enable PCIe link down reset, if link status changed from link up to
> > - * link down, this will reset MAC control registers and configuration
> > - * space.
> > - */
> > - writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
> > -
> > - /* De-assert PHY, PE, PIPE, MAC and configuration reset */
> > - val = readl(port->base + PCIE_RST_CTRL);
> > - val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
> > - PCIE_MAC_SRSTB | PCIE_CRSTB;
> > - writel(val, port->base + PCIE_RST_CTRL);
> > -
> > - /* Set up vendor ID and class code */
> > - if (soc->need_fix_class_id) {
> > - val = PCI_VENDOR_ID_MEDIATEK;
> > - writew(val, port->base + PCIE_CONF_VEND_ID);
> > -
> > - val = PCI_CLASS_BRIDGE_HOST;
> > - writew(val, port->base + PCIE_CONF_CLASS_ID);
> > - }
> > -
> > - /* 100ms timeout value should be enough for Gen1/2 training */
> > - err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
> > - !!(val & PCIE_PORT_LINKUP_V2), 20,
> > - 100 * USEC_PER_MSEC);
> > - if (err)
> > - return -ETIMEDOUT;
> > -
> > - /* Set INTx mask */
> > - val = readl(port->base + PCIE_INT_MASK);
> > - val &= ~INTX_MASK;
> > - writel(val, port->base + PCIE_INT_MASK);
> > -
> > - /* Set AHB to PCIe translation windows */
> > - size = mem->end - mem->start;
> > - val = lower_32_bits(mem->start) | AHB2PCIE_SIZE(fls(size));
> > - writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
> > -
> > - val = upper_32_bits(mem->start);
> > - writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
> > -
> > - /* Set PCIe to AXI translation memory space.*/
> > - val = fls(0xffffffff) | WIN_ENABLE;
> > - writel(val, port->base + PCIE_AXI_WINDOW0);
> > -
> > - return 0;
> > -}
> > -
> > static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
> > {
> > struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
> > @@ -643,8 +574,6 @@ static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port,
> > ret = mtk_pcie_allocate_msi_domains(port);
> > if (ret)
> > return ret;
> > -
> > - mtk_pcie_enable_msi(port);
> > }
> >
> > return 0;
> > @@ -711,6 +640,78 @@ static int mtk_pcie_setup_irq(struct mtk_pcie_port *port,
> > return 0;
> > }
> >
> > +static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
> > +{
> > + struct mtk_pcie *pcie = port->pcie;
> > + struct resource *mem = &pcie->mem;
> > + const struct mtk_pcie_soc *soc = port->pcie->soc;
> > + u32 val;
> > + size_t size;
> > + int err;
> > +
> > + /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
> > + if (pcie->base) {
> > + val = readl(pcie->base + PCIE_SYS_CFG_V2);
> > + val |= PCIE_CSR_LTSSM_EN(port->slot) |
> > + PCIE_CSR_ASPM_L1_EN(port->slot);
> > + writel(val, pcie->base + PCIE_SYS_CFG_V2);
> > + }
> > +
> > + /* Assert all reset signals */
> > + writel(0, port->base + PCIE_RST_CTRL);
> > +
> > + /*
> > + * Enable PCIe link down reset, if link status changed from link up to
> > + * link down, this will reset MAC control registers and configuration
> > + * space.
> > + */
> > + writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
> > +
> > + /* De-assert PHY, PE, PIPE, MAC and configuration reset */
> > + val = readl(port->base + PCIE_RST_CTRL);
> > + val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
> > + PCIE_MAC_SRSTB | PCIE_CRSTB;
> > + writel(val, port->base + PCIE_RST_CTRL);
> > +
> > + /* Set up vendor ID and class code */
> > + if (soc->need_fix_class_id) {
> > + val = PCI_VENDOR_ID_MEDIATEK;
> > + writew(val, port->base + PCIE_CONF_VEND_ID);
> > +
> > + val = PCI_CLASS_BRIDGE_HOST;
> > + writew(val, port->base + PCIE_CONF_CLASS_ID);
> > + }
> > +
> > + /* 100ms timeout value should be enough for Gen1/2 training */
> > + err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
> > + !!(val & PCIE_PORT_LINKUP_V2), 20,
> > + 100 * USEC_PER_MSEC);
> > + if (err)
> > + return -ETIMEDOUT;
> > +
> > + /* Set INTx mask */
> > + val = readl(port->base + PCIE_INT_MASK);
> > + val &= ~INTX_MASK;
> > + writel(val, port->base + PCIE_INT_MASK);
> > +
> > + if (IS_ENABLED(CONFIG_PCI_MSI))
> > + mtk_pcie_enable_msi(port);
> > +
> > + /* Set AHB to PCIe translation windows */
> > + size = mem->end - mem->start;
> > + val = lower_32_bits(mem->start) | AHB2PCIE_SIZE(fls(size));
> > + writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
> > +
> > + val = upper_32_bits(mem->start);
> > + writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
> > +
> > + /* Set PCIe to AXI translation memory space.*/
> > + val = fls(0xffffffff) | WIN_ENABLE;
> > + writel(val, port->base + PCIE_AXI_WINDOW0);
> > +
> > + return 0;
> > +}
> > +
> > static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus,
> > unsigned int devfn, int where)
> > {
> > --
> > 2.6.4
> >
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