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Date: Wed, 26 Sep 2018 17:36:32 +0800
From: Ryder Lee <ryder.lee@...iatek.com>
To: CK Hu <ck.hu@...iatek.com>
CC: Matthias Brugger <matthias.bgg@...il.com>,
Rob Herring <robh+dt@...nel.org>,
Sean Wang <sean.wang@...iatek.com>,
Roy Luo <cheng-hao.luo@...iatek.com>,
Weijie Gao <weijie.gao@...iatek.com>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-mediatek@...ts.infradead.org>,
chunhui dai <chunhui.dai@...iatek.com>,
Bibby Hsieh <bibby.hsieh@...iatek.com>
Subject: Re: [Resend PATCH 5/5] arm: dts: mt7623: add display subsystem
related device nodes
On Wed, 2018-09-26 at 17:20 +0800, CK Hu wrote:
> Hi, Ryder:
>
> More inline comment.
>
> On Wed, 2018-09-05 at 22:09 +0800, Ryder Lee wrote:
> > Add display subsystem related device nodes for MT7623.
> >
> > Cc: CK Hu <ck.hu@...iatek.com>
> > Signed-off-by: chunhui dai <chunhui.dai@...iatek.com>
> > Signed-off-by: Bibby Hsieh <bibby.hsieh@...iatek.com>
> > Signed-off-by: Ryder Lee <ryder.lee@...iatek.com>
> > ---
> > I forgot to sort nodes in my previous mail. Sorry for the inconvenience.
> >
> > This patch depends on the series: https://lkml.org/lkml/2018/9/5/223
> >
> > @Matthias,
> > I know you're working on broken MMSYS - just want to ask whether it's possible
> > to let the patch to go to your tree (if others are okay with it), and send a
> > fixup one for MT7623 MMSYS later?
> > ---
> > arch/arm/boot/dts/mt7623.dtsi | 177 ++++++++++++++++++++++++++
> > arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts | 83 ++++++++++++
> > arch/arm/boot/dts/mt7623n-rfb-emmc.dts | 83 ++++++++++++
> > 3 files changed, 343 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
> > index d01bdee..fdf9078 100644
> > --- a/arch/arm/boot/dts/mt7623.dtsi
> > +++ b/arch/arm/boot/dts/mt7623.dtsi
> > @@ -23,6 +23,11 @@
> > #address-cells = <2>;
> > #size-cells = <2>;
> >
> > + aliases {
> > + rdma0 = &rdma0;
> > + rdma1 = &rdma1;
> > + };
> > +
> > cpu_opp_table: opp-table {
> > compatible = "operating-points-v2";
> > opp-shared;
> > @@ -311,6 +316,25 @@
> > clock-names = "spi", "wrap";
> > };
> >
> > + mipi_tx0: mipi-dphy@...10000 {
> > + compatible = "mediatek,mt7623-mipi-tx",
> > + "mediatek,mt2701-mipi-tx";
> > + reg = <0 0x10010000 0 0x90>;
> > + clocks = <&clk26m>;
> > + clock-output-names = "mipi_tx0_pll";
> > + #clock-cells = <0>;
> > + #phy-cells = <0>;
> > + };
> > +
> > + cec: cec@...12000 {
> > + compatible = "mediatek,mt7623-cec",
> > + "mediatek,mt8173-cec";
> > + reg = <0 0x10012000 0 0xbc>;
> > + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
> > + clocks = <&infracfg CLK_INFRA_CEC>;
> > + status = "disabled";
> > + };
> > +
> > cir: cir@...13000 {
> > compatible = "mediatek,mt7623-cir";
> > reg = <0 0x10013000 0 0x1000>;
> > @@ -359,6 +383,18 @@
> > #clock-cells = <1>;
> > };
> >
> > + hdmi_phy: phy@...09100 {
> > + compatible = "mediatek,mt7623-hdmi-phy",
> > + "mediatek,mt2701-hdmi-phy";
> > + reg = <0 0x10209100 0 0x24>;
> > + clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
> > + clock-names = "pll_ref";
> > + clock-output-names = "hdmitx_dig_cts";
> > + #clock-cells = <0>;
> > + #phy-cells = <0>;
> > + status = "disabled";
> > + };
> > +
> > rng: rng@...0f000 {
> > compatible = "mediatek,mt7623-rng";
> > reg = <0 0x1020f000 0 0x1000>;
> > @@ -558,6 +594,16 @@
> > status = "disabled";
> > };
> >
> > + hdmiddc0: i2c@...13000 {
> > + compatible = "mediatek,mt7623-hdmi-ddc",
> > + "mediatek,mt8173-hdmi-ddc";
> > + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
> > + reg = <0 0x11013000 0 0x1C>;
> > + clocks = <&pericfg CLK_PERI_I2C3>;
> > + clock-names = "ddc-i2c";
> > + status = "disabled";
> > + };
> > +
> > nor_flash: spi@...14000 {
> > compatible = "mediatek,mt7623-nor",
> > "mediatek,mt8173-nor";
> > @@ -732,6 +778,84 @@
> > #clock-cells = <1>;
> > };
> >
> > + display_components: dispsys@...00000 {
> > + compatible = "mediatek,mt7623-mmsys",
> > + "mediatek,mt2701-mmsys";
> > + reg = <0 0x14000000 0 0x1000>;
> > + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
> > + };
> > +
> > + ovl@...07000 {
> > + compatible = "mediatek,mt7623-disp-ovl",
> > + "mediatek,mt2701-disp-ovl";
> > + reg = <0 0x14007000 0 0x1000>;
> > + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>;
> > + clocks = <&mmsys CLK_MM_DISP_OVL>;
> > + iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>;
> > + mediatek,larb = <&larb0>;
> > + };
> > +
> > + rdma0: rdma@...08000 {
> > + compatible = "mediatek,mt7623-disp-rdma",
> > + "mediatek,mt2701-disp-rdma";
> > + reg = <0 0x14008000 0 0x1000>;
> > + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
> > + clocks = <&mmsys CLK_MM_DISP_RDMA>;
> > + iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>;
> > + mediatek,larb = <&larb0>;
> > + };
> > +
> > + wdma@...09000 {
> > + compatible = "mediatek,mt7623-disp-wdma",
> > + "mediatek,mt2701-disp-wdma";
> > + reg = <0 0x14009000 0 0x1000>;
> > + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>;
> > + clocks = <&mmsys CLK_MM_DISP_WDMA>;
> > + iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>;
> > + mediatek,larb = <&larb0>;
> > + };
> > +
> > + bls: pwm@...0a000 {
> > + compatible = "mediatek,mt7623-disp-pwm",
> > + "mediatek,mt2701-disp-pwm";
> > + reg = <0 0x1400a000 0 0x1000>;
> > + #pwm-cells = <2>;
> > + clocks = <&mmsys CLK_MM_MDP_BLS_26M>,
> > + <&mmsys CLK_MM_DISP_BLS>;
> > + clock-names = "main", "mm";
> > + status = "disabled";
> > + };
> > +
> > + color@...0b000 {
> > + compatible = "mediatek,mt7623-disp-color",
> > + "mediatek,mt2701-disp-color";
> > + reg = <0 0x1400b000 0 0x1000>;
> > + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW>;
> > + clocks = <&mmsys CLK_MM_DISP_COLOR>;
> > + };
> > +
> > + dsi: dsi@...0c000 {
> > + compatible = "mediatek,mt7623-dsi",
> > + "mediatek,mt2701-dsi";
> > + reg = <0 0x1400c000 0 0x1000>;
> > + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW>;
> > + clocks = <&mmsys CLK_MM_DSI_ENGINE>,
> > + <&mmsys CLK_MM_DSI_DIG>,
> > + <&mipi_tx0>;
> > + clock-names = "engine", "digital", "hs";
> > + phys = <&mipi_tx0>;
> > + phy-names = "dphy";
> > + status = "disabled";
> > + };
> > +
> > + mutex: mutex@...0e000 {
> > + compatible = "mediatek,mt7623-disp-mutex",
> > + "mediatek,mt2701-disp-mutex";
> > + reg = <0 0x1400e000 0 0x1000>;
> > + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
> > + clocks = <&mmsys CLK_MM_MUTEX_32K>;
> > + };
> > +
> > larb0: larb@...10000 {
> > compatible = "mediatek,mt7623-smi-larb",
> > "mediatek,mt2701-smi-larb";
> > @@ -744,6 +868,44 @@
> > power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
> > };
> >
> > + rdma1: rdma@...12000 {
> > + compatible = "mediatek,mt7623-disp-rdma",
> > + "mediatek,mt2701-disp-rdma";
> > + reg = <0 0x14012000 0 0x1000>;
> > + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;
> > + clocks = <&mmsys CLK_MM_DISP_RDMA1>;
> > + iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>;
> > + mediatek,larb = <&larb0>;
> > + };
> > +
> > + dpi0: dpi@...14000 {
> > + compatible = "mediatek,mt7623-dpi",
> > + "mediatek,mt2701-dpi";
> > + reg = <0 0x14014000 0 0x1000>;
> > + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
> > + clocks = <&mmsys CLK_MM_DPI1_DIGL>,
> > + <&mmsys CLK_MM_DPI1_ENGINE>,
> > + <&topckgen CLK_TOP_TVDPLL>;
> > + clock-names = "pixel", "engine", "pll";
> > + status = "disabled";
> > + };
> > +
> > + hdmi0: hdmi@...15000 {
> > + compatible = "mediatek,mt7623-hdmi",
> > + "mediatek,mt8173-hdmi";
> > + reg = <0 0x14015000 0 0x400>;
> > + clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
> > + <&mmsys CLK_MM_HDMI_PLL>,
> > + <&mmsys CLK_MM_HDMI_AUDIO>,
> > + <&mmsys CLK_MM_HDMI_SPDIF>;
> > + clock-names = "pixel", "pll", "bclk", "spdif";
> > + phys = <&hdmi_phy>;
> > + phy-names = "hdmi";
> > + mediatek,syscon-hdmi = <&mmsys 0x900>;
> > + cec = <&cec>;
> > + status = "disabled";
> > + };
> > +
> > imgsys: syscon@...00000 {
> > compatible = "mediatek,mt7623-imgsys",
> > "mediatek,mt2701-imgsys",
> > @@ -1071,6 +1233,21 @@
> > };
> > };
> >
> > + hdmi_pins_a: hdmi-default {
> > + pins-hdmi {
> > + pinmux = <MT7623_PIN_123_HTPLG_FUNC_HTPLG>;
> > + input-enable;
> > + bias-pull-down;
> > + };
> > + };
> > +
> > + hdmi_ddc_pins_a: hdmi_ddc-default {
> > + pins-hdmi-ddc {
> > + pinmux = <MT7623_PIN_124_GPIO124_FUNC_HDMISCK>,
> > + <MT7623_PIN_125_GPIO125_FUNC_HDMISD>;
> > + };
> > + };
> > +
> > i2c0_pins_a: i2c0-default {
> > pins-i2c0 {
> > pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,
> > diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
> > index 2b760f9..dbce86b 100644
> > --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
> > +++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
> > @@ -21,6 +21,19 @@
> > stdout-path = "serial2:115200n8";
> > };
> >
> > + connector {
> > + compatible = "hdmi-connector";
> > + label = "hdmi";
> > + type = "d";
> > + ddc-i2c-bus = <&hdmiddc0>;
> > +
> > + port {
> > + hdmi_connector_in: endpoint {
> > + remote-endpoint = <&hdmi0_out>;
> > + };
> > + };
> > + };
> > +
> > cpus {
> > cpu@0 {
> > proc-supply = <&mt6323_vproc_reg>;
> > @@ -114,10 +127,24 @@
> > };
> > };
> >
> > +&bls {
> > + status = "okay";
> > +
> > + port {
> > + bls_out: endpoint {
> > + remote-endpoint = <&dpi0_in>;
> > + };
> > + };
> > +};
> > +
> > &btif {
> > status = "okay";
> > };
> >
> > +&cec {
> > + status = "okay";
> > +};
> > +
> > &cir {
> > pinctrl-names = "default";
> > pinctrl-0 = <&cir_pins_a>;
> > @@ -128,6 +155,26 @@
> > status = "okay";
> > };
> >
> > +&dpi0 {
> > + status = "okay";
> > +
> > + ports {
> > + port@0 {
> > + reg = <0>;
> > + dpi0_out: endpoint {
> > + remote-endpoint = <&hdmi0_in>;
> > + };
> > + };
> > +
> > + port@1 {
> > + reg = <1>;
> > + dpi0_in: endpoint {
> > + remote-endpoint = <&bls_out>;
> > + };
> > + };
> > + };
>
> This part is different with binding
> (Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt), I
> think you should modify the binding document.
> > +};
> > +
> > ð {
> > status = "okay";
> >
> > @@ -199,6 +246,42 @@
> > };
> > };
> >
> > +&hdmi0 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&hdmi_pins_a>;
> > + status = "okay";
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + port@0 {
> > + reg = <0>;
> > + hdmi0_in: endpoint {
> > + remote-endpoint = <&dpi0_out>;
> > + };
> > + };
> > +
> > + port@1 {
> > + reg = <1>;
> > + hdmi0_out: endpoint {
> > + remote-endpoint = <&hdmi_connector_in>;
> > + };
> > + };
> > + };
> > +};
> > +
> > +&hdmiddc0 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&hdmi_ddc_pins_a>;
> > + status = "okay";
> > +};
> > +
> > +&hdmi_phy {
> > + mediatek,ibias = <0xa>;
> > + mediatek,ibias_up = <0x1c>;
> > + status = "okay";
> > +};
> > +
> > &i2c0 {
> > pinctrl-names = "default";
> > pinctrl-0 = <&i2c0_pins_a>;
> > diff --git a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts
> > index b760613..bdf9010 100644
> > --- a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts
> > +++ b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts
> > @@ -24,6 +24,19 @@
> > stdout-path = "serial2:115200n8";
> > };
> >
> > + connector {
> > + compatible = "hdmi-connector";
> > + label = "hdmi";
> > + type = "d";
> > + ddc-i2c-bus = <&hdmiddc0>;
> > +
> > + port {
> > + hdmi_connector_in: endpoint {
> > + remote-endpoint = <&hdmi0_out>;
> > + };
> > + };
> > + };
> > +
> > cpus {
> > cpu@0 {
> > proc-supply = <&mt6323_vproc_reg>;
> > @@ -106,10 +119,24 @@
> > };
> > };
> >
> > +&bls {
> > + status = "okay";
> > +
> > + port {
> > + bls_out: endpoint {
> > + remote-endpoint = <&dpi0_in>;
> > + };
> > + };
>
> This part is different with binding
> (Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt),
> I think you should modify the binding document.
>
> Regards,
> CK
Okay, we will update mediatek,disp.txt.
Ryder
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