linux-kernel - Re: [PATCH v4] ARM: dts: dra7: Fix up unaligned access setting for PCIe EP

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Date:   Fri, 28 Sep 2018 10:26:30 -0700
From:   Tony Lindgren <tony@...mide.com>
To:     Vignesh R <vigneshr@...com>
Cc:     "linux-omap@...r.kernel.org" <linux-omap@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v4] ARM: dts: dra7: Fix up unaligned access setting for
 PCIe EP

* Vignesh R <vigneshr@...com> [180928 05:31]:
> 
> 
> On Wednesday 26 September 2018 10:57 PM, Tony Lindgren wrote:
> > * Vignesh R <vigneshr@...com> [180924 22:25]:
> >> Bit positions of PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE and
> >> PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE in CTRL_CORE_SMA_SW_7 are
> >> incorrectly documented in the TRM. In fact, the bit positions are
> >> swapped. Update the DT bindings for PCIe EP to reflect the same.
> >>
> >> Fixes: d23f3839fe97 ("ARM: dts: DRA7: Add pcie1 dt node for EP mode")
> >> Cc: stable@...r.kernel.org
> >> Signed-off-by: Vignesh R <vigneshr@...com>
> >> ---
> >>
> >> This patch is split from v3 here:
> >> https://lore.kernel.org/patchwork/cover/967020/
> >> Patch can be applied standalone and has no dependencies on other patches
> >> in v3.
> > 
> > Hmm is this needed for v4.19-rc cycle or can this wait for
> > v4.20 merge window?
> > 
> 
> v4.20 should be fine.

OK thanks applying into omap-for-v4.20/dt then.

Tony