lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Sat, 29 Sep 2018 14:56:13 +0200
From:   Matthias Brugger <matthias.bgg@...il.com>
To:     Chaotian Jing <chaotian.jing@...iatek.com>,
        Ulf Hansson <ulf.hansson@...aro.org>
Cc:     Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Ryder Lee <ryder.lee@...iatek.com>,
        Wolfram Sang <wsa+renesas@...g-engineering.com>,
        Sean Wang <sean.wang@...iatek.com>, linux-mmc@...r.kernel.org,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org,
        srv_heupstream@...iatek.com
Subject: Re: [PATCH v1 2/2] mmc: mediatek: add bus_clk control



On 29/09/2018 04:29, Chaotian Jing wrote:
> when gate MSDC0_HCLK, access register will hang, even the MSDC driver
> will never accessing register after HCLK was gated, but for safety, need
> gate the bus_clk(which used to access register) too.
> 
> Signed-off-by: Chaotian Jing <chaotian.jing@...iatek.com>
> ---
>  drivers/mmc/host/mtk-sd.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
> index 0484138..1c1c967 100644
> --- a/drivers/mmc/host/mtk-sd.c
> +++ b/drivers/mmc/host/mtk-sd.c
> @@ -387,6 +387,7 @@ struct msdc_host {
>  
>  	struct clk *src_clk;	/* msdc source clock */
>  	struct clk *h_clk;      /* msdc h_clk */
> +	struct clk *bus_clk;	/* bus clock which used to access register */
>  	struct clk *src_clk_cg; /* msdc source clock control gate */
>  	u32 mclk;		/* mmc subsystem clock frequency */
>  	u32 src_clk_freq;	/* source clock frequency */
> @@ -660,12 +661,14 @@ static void msdc_gate_clock(struct msdc_host *host)
>  {
>  	clk_disable_unprepare(host->src_clk_cg);
>  	clk_disable_unprepare(host->src_clk);
> +	clk_disable_unprepare(host->bus_clk);
>  	clk_disable_unprepare(host->h_clk);
>  }
>  
>  static void msdc_ungate_clock(struct msdc_host *host)
>  {
>  	clk_prepare_enable(host->h_clk);
> +	clk_prepare_enable(host->bus_clk);
>  	clk_prepare_enable(host->src_clk);
>  	clk_prepare_enable(host->src_clk_cg);
>  	while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
> @@ -1900,6 +1903,9 @@ static int msdc_drv_probe(struct platform_device *pdev)
>  		goto host_free;
>  	}
>  
> +	host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk");
> +	if (IS_ERR(host->bus_clk))
> +		host->bus_clk = NULL;

That means the bus_clk is not requiered, even for mt2712, although the binding
says so. Not sure if this is good enough or if we want to enforce the driver to
actually error out, when the clock is not present in a mt2712 DTS.

I suppose that's up to the maintainer :)

Regards,
Matthias

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ