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Message-ID: <1538188195-3608-1-git-send-email-chaotian.jing@mediatek.com>
Date: Sat, 29 Sep 2018 10:29:54 +0800
From: Chaotian Jing <chaotian.jing@...iatek.com>
To: Ulf Hansson <ulf.hansson@...aro.org>
CC: Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Matthias Brugger <matthias.bgg@...il.com>,
Chaotian Jing <chaotian.jing@...iatek.com>,
Ryder Lee <ryder.lee@...iatek.com>,
Wolfram Sang <wsa+renesas@...g-engineering.com>,
Sean Wang <sean.wang@...iatek.com>,
<linux-mmc@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-mediatek@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <srv_heupstream@...iatek.com>
Subject: [PATCH v1 1/2] mmc: dt-bindings: add "bus-clk" for MT2712
On MT2712 MSDC0/3, HCLK/bus-clk need gate/ungate together,
or will hang when access MSDC register.
Signed-off-by: Chaotian Jing <chaotian.jing@...iatek.com>
---
Documentation/devicetree/bindings/mmc/mtk-sd.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt
index f33467a..f2208f4 100644
--- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt
+++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt
@@ -22,6 +22,7 @@ Required properties:
"source" - source clock (required)
"hclk" - HCLK which used for host (required)
"source_cg" - independent source clock gate (required for MT2712)
+ "bus_clk" - bus clock used for internal register access (required for MT2712 MSDC0/3)
- pinctrl-names: should be "default", "state_uhs"
- pinctrl-0: should contain default/high speed pin ctrl
- pinctrl-1: should contain uhs mode pin ctrl
--
1.8.1.1.dirty
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