[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20180930141510.2690-3-yasha.che3@gmail.com>
Date: Sun, 30 Sep 2018 17:15:07 +0300
From: Yasha Cherikovsky <yasha.che3@...il.com>
To: Ralf Baechle <ralf@...ux-mips.org>,
Paul Burton <paul.burton@...s.com>,
James Hogan <jhogan@...nel.org>, linux-mips@...ux-mips.org
Cc: Yasha Cherikovsky <yasha.che3@...il.com>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: [RFC 2/5] dt-binding: timer: Document RTL8186 SoC DT bindings
This patch adds device tree binding doc for the
Realtek RTL8186 SoC timer controller.
Signed-off-by: Yasha Cherikovsky <yasha.che3@...il.com>
Cc: Rob Herring <robh+dt@...nel.org>
Cc: Mark Rutland <mark.rutland@....com>
Cc: Daniel Lezcano <daniel.lezcano@...aro.org>
Cc: Thomas Gleixner <tglx@...utronix.de>
Cc: Ralf Baechle <ralf@...ux-mips.org>
Cc: Paul Burton <paul.burton@...s.com>
Cc: James Hogan <jhogan@...nel.org>
Cc: devicetree@...r.kernel.org
Cc: linux-mips@...ux-mips.org
Cc: linux-kernel@...r.kernel.org
---
.../bindings/timer/realtek,rtl8186-timer.txt | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/realtek,rtl8186-timer.txt
diff --git a/Documentation/devicetree/bindings/timer/realtek,rtl8186-timer.txt b/Documentation/devicetree/bindings/timer/realtek,rtl8186-timer.txt
new file mode 100644
index 000000000000..eaa6292c16e0
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/realtek,rtl8186-timer.txt
@@ -0,0 +1,17 @@
+Realtek RTL8186 SoC timer
+
+Required properties:
+
+- compatible : Should be "realtek,rtl8186-timer".
+- reg : Specifies base physical address and size of the registers.
+- interrupts : The interrupt number of the timer.
+- clocks: phandle to the source clock (usually a 22 MHz fixed clock)
+
+Example:
+
+timer {
+ compatible = "realtek,rtl8186-timer";
+ reg = <0x1d010050 0x30>;
+ interrupts = <0>;
+ clocks = <&sysclk>;
+};
--
2.19.0
Powered by blists - more mailing lists