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Message-ID: <alpine.DEB.2.21.1810022104480.1435@nanos.tec.linutronix.de>
Date:   Tue, 2 Oct 2018 21:10:36 +0200 (CEST)
From:   Thomas Gleixner <tglx@...utronix.de>
To:     Tim Chen <tim.c.chen@...ux.intel.com>
cc:     Jiri Kosina <jikos@...nel.org>,
        Tom Lendacky <thomas.lendacky@....com>,
        Ingo Molnar <mingo@...hat.com>,
        Peter Zijlstra <peterz@...radead.org>,
        Josh Poimboeuf <jpoimboe@...hat.com>,
        Andrea Arcangeli <aarcange@...hat.com>,
        David Woodhouse <dwmw@...zon.co.uk>,
        Andi Kleen <ak@...ux.intel.com>,
        Dave Hansen <dave.hansen@...el.com>,
        Casey Schaufler <casey.schaufler@...el.com>,
        Asit Mallick <asit.k.mallick@...el.com>,
        Arjan van de Ven <arjan@...ux.intel.com>,
        Jon Masters <jcm@...hat.com>, linux-kernel@...r.kernel.org,
        x86@...nel.org
Subject: Re: [Patch v2 2/4] x86/speculation: Provide application property
 based STIBP protection

On Tue, 25 Sep 2018, Tim Chen wrote:

> This patch provides an application property based spectre_v2

# git grep 'This patch' Documentation/process/

> protection with STIBP against attack from another app from

s/app/application/ please. This is not android.

> a sibling hyper-thread.  For security sensitive non-dumpable
> app, STIBP will be turned on before switching to it for Intel
> processors vulnerable to spectre_v2.

What has this to do with Intel processors?

> -static __always_inline void intel_set_ssb_state(unsigned long tifn)
> +static __always_inline void set_spec_ctrl_state(unsigned long tifn)
>  {
> -	u64 msr = x86_spec_ctrl_base | ssbd_tif_to_spec_ctrl(tifn);
> +	u64 msr = x86_spec_ctrl_base;
> +
> +	if (static_cpu_has(X86_FEATURE_SSBD))
> +		msr |= ssbd_tif_to_spec_ctrl(tifn);
> +
> +	if (cpu_smt_control == CPU_SMT_ENABLED)
> +		msr |= stibp_tif_to_spec_ctrl(tifn);

Oh no. We are not adding yet another conditional into switch to. Either
that's done unconditionally or this wants to have a static key.

>  	wrmsrl(MSR_IA32_SPEC_CTRL, msr);

Thanks,

	tglx

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