lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <tip-2647c43c7f3ba4b752bfce261d53b16e2f5bc9e3@git.kernel.org>
Date:   Tue, 2 Oct 2018 12:34:26 -0700
From:   tip-bot for Mike Travis <tipbot@...or.com>
To:     linux-tip-commits@...r.kernel.org
Cc:     mingo@...nel.org, peterz@...radead.org, rajvi.jingar@...el.com,
        douly.fnst@...fujitsu.com, mike.travis@....com,
        len.brown@...el.com, gxm.linux.kernel@...il.com,
        pasha.tatashin@...cle.com, linux-kernel@...r.kernel.org,
        kstewart@...uxfoundation.org, sivanich@....com,
        russ.anderson@....com, dimitri.sivanich@....com,
        tglx@...utronix.de, hpa@...or.com, pombredanne@...b.com,
        bp@...en8.de, hedi.berriche@....com, gregkh@...uxfoundation.org,
        rja@....com
Subject: [tip:x86/urgent] x86/tsc: Fix UV TSC initialization

Commit-ID:  2647c43c7f3ba4b752bfce261d53b16e2f5bc9e3
Gitweb:     https://git.kernel.org/tip/2647c43c7f3ba4b752bfce261d53b16e2f5bc9e3
Author:     Mike Travis <mike.travis@....com>
AuthorDate: Tue, 2 Oct 2018 13:01:46 -0500
Committer:  Thomas Gleixner <tglx@...utronix.de>
CommitDate: Tue, 2 Oct 2018 21:29:16 +0200

x86/tsc: Fix UV TSC initialization

The recent rework of the TSC calibration code introduced a regression on UV
systems as it added a call to tsc_early_init() which initializes the TSC
ADJUST values before acpi_boot_table_init().  In the case of UV systems,
that is a necessary step that calls uv_system_init().  This informs
tsc_sanitize_first_cpu() that the kernel runs on a platform with async TSC
resets as documented in commit 341102c3ef29 ("x86/tsc: Add option that TSC
on Socket 0 being non-zero is valid")

Fix it by skipping the early tsc initialization on UV systems and let TSC
init tests take place later in tsc_init().

Fixes: cf7a63ef4e02 ("x86/tsc: Calibrate tsc only once")
Suggested-by: Hedi Berriche <hedi.berriche@....com>
Signed-off-by: Mike Travis <mike.travis@....com>
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Reviewed-by: Russ Anderson <rja@....com>
Reviewed-by: Dimitri Sivanich <sivanich@....com>
Cc: "H. Peter Anvin" <hpa@...or.com>
Cc: Russ Anderson <russ.anderson@....com>
Cc: Dimitri Sivanich <dimitri.sivanich@....com>
Cc: Borislav Petkov <bp@...en8.de>
Cc: Kate Stewart <kstewart@...uxfoundation.org>
Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
Cc: Philippe Ombredanne <pombredanne@...b.com>
Cc: Pavel Tatashin <pasha.tatashin@...cle.com>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Len Brown <len.brown@...el.com>
Cc: Dou Liyang <douly.fnst@...fujitsu.com>
Cc: Xiaoming Gao <gxm.linux.kernel@...il.com>
Cc: Rajvi Jingar <rajvi.jingar@...el.com>
Link: https://lkml.kernel.org/r/20181002180144.923579706@stormcage.americas.sgi.com

---
 arch/x86/kernel/tsc.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 6490f618e096..b52bd2b6cdb4 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -26,6 +26,7 @@
 #include <asm/apic.h>
 #include <asm/intel-family.h>
 #include <asm/i8259.h>
+#include <asm/uv/uv.h>
 
 unsigned int __read_mostly cpu_khz;	/* TSC clocks / usec, not used here */
 EXPORT_SYMBOL(cpu_khz);
@@ -1433,6 +1434,9 @@ void __init tsc_early_init(void)
 {
 	if (!boot_cpu_has(X86_FEATURE_TSC))
 		return;
+	/* Don't change UV TSC multi-chassis synchronization */
+	if (is_early_uv_system())
+		return;
 	if (!determine_cpu_tsc_frequencies(true))
 		return;
 	loops_per_jiffy = get_loops_per_jiffy();

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ