linux-kernel - Re: [Problem] Cache line starvation

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Message-ID: <20181003082842.GN26858@hirez.programming.kicks-ass.net>
Date:   Wed, 3 Oct 2018 10:28:42 +0200
From:   Peter Zijlstra <peterz@...radead.org>
To:     Thomas Gleixner <tglx@...utronix.de>
Cc:     Catalin Marinas <catalin.marinas@....com>, bigeasy@...utronix.de,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        daniel.wagner@...mens.com, Will Deacon <will.deacon@....com>,
        x86@...nel.org, Linus Torvalds <torvalds@...ux-foundation.org>,
        "H. Peter Anvin" <hpa@...or.com>, boqun.feng@...il.com,
        Paul McKenney <paulmck@...ux.vnet.ibm.com>
Subject: Re: [Problem] Cache line starvation

On Wed, Oct 03, 2018 at 10:07:05AM +0200, Thomas Gleixner wrote:
> On Wed, 3 Oct 2018, Catalin Marinas wrote:
> 
> > On Fri, 21 Sep 2018 at 13:22, Peter Zijlstra <peterz@...radead.org> wrote:
> > > On Fri, Sep 21, 2018 at 02:02:26PM +0200, Sebastian Andrzej Siewior wrote:
> > > > We reproducibly observe cache line starvation on a Core2Duo E6850 (2
> > > > cores), a i5-6400 SKL (4 cores) and on a NXP LS2044A ARM Cortex-A72 (4
> > > > cores).

> Except that the ARM64 ticket locks are not preventing the starvation
> issue. Neither do the qrlocks on ARM64 on later kernels.

That A72 is ARMv8-A afaict, that doesn't have the fancy LSE bits (which
are new in ARMv8.1) on and thus ends up using LL/SC. And LL/SC has
similar issues as cmpxchg loops.

AFAICT Cortex-A75 is the first that has LSE on (that's an ARMv8.2-A).