linux-kernel - Re: [PATCH] perf/x86/intel: Add counter freezing quirk for Goldmont

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Message-ID: <alpine.DEB.2.21.1810031550550.23677@nanos.tec.linutronix.de>
Date:   Wed, 3 Oct 2018 15:55:29 +0200 (CEST)
From:   Thomas Gleixner <tglx@...utronix.de>
To:     "Liang, Kan" <kan.liang@...ux.intel.com>
cc:     Peter Zijlstra <peterz@...radead.org>, mingo@...hat.com,
        acme@...nel.org, LKML <linux-kernel@...r.kernel.org>,
        eranian@...gle.com, ak@...ux.intel.com,
        alexander.shishkin@...ux.intel.com, x86@...nel.org
Subject: Re: [PATCH] perf/x86/intel: Add counter freezing quirk for
 Goldmont

On Wed, 3 Oct 2018, Liang, Kan wrote:
> On 10/3/2018 2:10 AM, Thomas Gleixner wrote:
> > There is another variant of model/stepping micro code verification code in
> > intel_snb_pebs_broken(). Can we please make this table based and use a
> > common function? That's certainly not the last quirk we're going to have.
> > 
> > We already have a table based variant of ucode checking in
> > bad_spectre_microcode(). It's trivial enough to generalize that.
> > 
> 
> Sure, I will generalize the bad_spectre_microcode(), rename it to
> is_bad_intel_microcode(), and move it to
> arch\x86\kernel\cpu\microcode\intel.c.

I suggest: is_bad_microcode() and have it in cpu/microcode/core.c unless
you are claiming that bad microcode() is an intel only feature.

> The spectre code and perf code will share the generalized function.

Right. The tables stay in the calling code of course.

Thanks,

	tglx