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Date: Thu, 4 Oct 2018 21:26:02 +0000
From: Jolly Shah <JOLLYS@...inx.com>
To: Rob Herring <robh@...nel.org>
CC: Matthias Brugger <matthias.bgg@...il.com>,
Andy Gross <andy.gross@...aro.org>,
Shawn Guo <shawnguo@...nel.org>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Sean Wang <sean.wang@...iatek.com>,
Marek Szyprowski <m.szyprowski@...sung.com>,
Michal Simek <michals@...inx.com>,
Mark Rutland <mark.rutland@....com>,
Rajan Vaja <RAJANV@...inx.com>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v2 1/3] dt-bindings: power: Add ZynqMP power domain
bindings
Hi Rob,
> -----Original Message-----
> From: Rob Herring [mailto:robh@...nel.org]
> Sent: Tuesday, September 25, 2018 9:15 AM
> To: Jolly Shah <JOLLYS@...inx.com>
> Cc: Matthias Brugger <matthias.bgg@...il.com>; Andy Gross
> <andy.gross@...aro.org>; Shawn Guo <shawnguo@...nel.org>; Geert
> Uytterhoeven <geert+renesas@...der.be>; Bjorn Andersson
> <bjorn.andersson@...aro.org>; Sean Wang <sean.wang@...iatek.com>;
> Marek Szyprowski <m.szyprowski@...sung.com>; Michal Simek
> <michals@...inx.com>; Mark Rutland <mark.rutland@....com>; Rajan Vaja
> <RAJANV@...inx.com>; devicetree@...r.kernel.org; moderated
> list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE <linux-arm-
> kernel@...ts.infradead.org>; linux-kernel@...r.kernel.org
> Subject: Re: [PATCH v2 1/3] dt-bindings: power: Add ZynqMP power domain
> bindings
>
> On Thu, Sep 13, 2018 at 12:51 PM Jolly Shah <JOLLYS@...inx.com> wrote:
> >
> > Hi Rob,
> >
> > > -----Original Message-----
> > > From: Rob Herring [mailto:robh@...nel.org]
> > > Sent: Monday, August 20, 2018 12:46 PM
> > > To: Jolly Shah <JOLLYS@...inx.com>
> > > Cc: matthias.bgg@...il.com; andy.gross@...aro.org;
> > > shawnguo@...nel.org;
> > > geert+renesas@...der.be; bjorn.andersson@...aro.org;
> > > sean.wang@...iatek.com; m.szyprowski@...sung.com; Michal Simek
> > > <michals@...inx.com>; mark.rutland@....com; Rajan Vaja
> > > <RAJANV@...inx.com>; devicetree@...r.kernel.org; linux-arm-
> > > kernel@...ts.infradead.org; linux-kernel@...r.kernel.org; Rajan Vaja
> > > <RAJANV@...inx.com>; Jolly Shah <JOLLYS@...inx.com>
> > > Subject: Re: [PATCH v2 1/3] dt-bindings: power: Add ZynqMP power
> > > domain bindings
> > >
> > > On Thu, Aug 16, 2018 at 12:21:42PM -0700, Jolly Shah wrote:
> > > > From: Rajan Vaja <rajan.vaja@...inx.com>
> > > >
> > > > Add documentation to describe ZynqMP power domain bindings.
> > > >
> > > > Signed-off-by: Rajan Vaja <rajan.vaja@...inx.com>
> > > > Signed-off-by: Jolly Shah <jollys@...inx.com>
> > > > ---
> > > > .../firmware/xilinx/xlnx,zynqmp-firmware.txt | 47
> > > ++++++++++++++++++++++
> > >
> > > This should be with all the other power domain bindings.
> > >
> > > > 1 file changed, 47 insertions(+)
> > > >
> > > > diff --git
> > > > a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-fi
> > > > rmwa
> > > > re.txt
> > > > b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-fi
> > > > rmwa
> > > > re.txt
> > > > index d215d15..5fa10a0 100644
> > > > ---
> > > > a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-fi
> > > > rmwa
> > > > re.txt
> > > > +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqm
> > > > +++ p-fi
> > > > +++ rmware.txt
> > > > @@ -64,6 +64,29 @@ Output clocks are registered based on clock
> > > > information received from firmware. Output clocks indexes are
> > > > mentioned in include/dt-bindings/clock/xlnx,zynqmp-clk.h.
> > > >
> > > > +-----------------------------------------------------------
> > > > +Device Tree Bindings for the Xilinx Zynq MPSoC PM domains
> > > > +-----------------------------------------------------------
> > > > +The binding for zynqmp-power-controller follow the common generic
> > > > +PM domain binding[1].
> > > > +
> > > > +[1] Documentation/devicetree/bindings/power/power_domain.txt
> > > > +
> > > > +== Zynq MPSoC Generic PM Domain Node ==
> > > > +
> > > > +Required properties:
> > > > + - compatible: Must be: "xlnx,zynqmp-power-controller"
> > > > +
> > > > +This node contains a number of subnodes, each representing a
> > > > +single PM domain that PM domain consumer devices reference.
> > > > +
> > > > +== PM Domain Nodes ==
> > > > +
> > > > +Required properties:
> > > > + - #power-domain-cells: Number of cells in a PM domain specifier. Must
> > > be 0.
> > > > + - pd-id: Domain identifier as defined by platform firmware.
> > > > + This identifier is passed to the PM firmware.
> > >
> > > Make this a cell for the power domain consumer.
> > [Jolly] We have more than one Ids for GPU device. Also they don't have
> > parent child relationship and hence are defined as flat hierarchy.
> > (shown in example below)
>
> Then the gpu node should have:
>
> power-domains = <&pd 58 &pd 20 &pd 21>;
>
> Also, for this and the firmware reset binding, there is no reason that I see to
> make these all subnodes. A single firmware node can be a provider of multiple
> functions. You only need child nodes if the sub-functions have their own
> resources (clks, irqs, etc.). IOW, don't create nodes just because you want to
> instantiate drivers that way. DT is not the only way to instantiate devices for
> drivers.
>
Got it. Pushed v3 with suggested changes. Please review.
> Rob
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