[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20181007093905.11253-25-jernej.skrabec@siol.net>
Date: Sun, 7 Oct 2018 11:39:00 +0200
From: Jernej Skrabec <jernej.skrabec@...l.net>
To: maxime.ripard@...tlin.com, wens@...e.org
Cc: robh+dt@...nel.org, sboyd@...nel.org, airlied@...ux.ie,
architt@...eaurora.org, a.hajda@...sung.com,
Laurent.pinchart@...asonboard.com, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org, dri-devel@...ts.freedesktop.org,
linux-sunxi@...glegroups.com
Subject: [PATCH v2 24/29] drm/sun4i: Initialize registers in tcon-top driver
It turns out that TCON TOP registers in H6 SoC have non-zero reset
value. This may cause issues if bits are not changed during
configuration.
To prevent that, initialize registers to 0.
Signed-off-by: Jernej Skrabec <jernej.skrabec@...l.net>
---
drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
index 3040a79f298f..37158548b447 100644
--- a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
+++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
@@ -167,6 +167,13 @@ static int sun8i_tcon_top_bind(struct device *dev, struct device *master,
goto err_assert_reset;
}
+ /*
+ * At least on H6, some registers have some bits set by default
+ * which may cause issues. Clear them here.
+ */
+ writel(0, regs + TCON_TOP_PORT_SEL_REG);
+ writel(0, regs + TCON_TOP_GATE_SRC_REG);
+
/*
* TCON TOP has two muxes, which select parent clock for each TCON TV
* channel clock. Parent could be either TCON TV or TVE clock. For now
--
2.19.0
Powered by blists - more mailing lists