| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <153896666821.119890.13143150697797456341@swboyd.mtv.corp.google.com>
Date: Sun, 07 Oct 2018 19:44:28 -0700
From: Stephen Boyd <sboyd@...nel.org>
To: Michael Turquette <mturquette@...libre.com>,
Taniya Das <tdas@...eaurora.org>
Cc: Andy Gross <andy.gross@...aro.org>,
David Brown <david.brown@...aro.org>,
Rajendra Nayak <rnayak@...eaurora.org>,
linux-arm-msm@...r.kernel.org, linux-soc@...r.kernel.org,
linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
Taniya Das <tdas@...eaurora.org>
Subject: Re: [PATCH v6] clk: qcom: Add lpass clock controller driver for SDM845
Quoting Taniya Das (2018-10-04 05:02:26)
> Add support for the lpass clock controller found on SDM845 based devices.
> This would allow lpass peripheral loader drivers to control the clocks to
> bring the subsystem out of reset.
> LPASS clocks present on the global clock controller would be registered
> with the clock framework based on the device tree flag. Also do not gate
> these clocks if they are left unused.
Why not gate them? This statement states what the code is doing, not why
it's doing it which is the more crucial information that should be
described in the commit text. Also, please add a comment about it to the
code next to the flag.
I am concerned that it doesn't make any sense though, so probably it
shouldn't be marked as CLK_IGNORE_UNUSED and it's papering over some
other larger bug that needs to be fixed.
>
> Signed-off-by: Taniya Das <tdas@...eaurora.org>
> ---
> diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
> index 08d593e..6379b8b 100644
> --- a/drivers/clk/qcom/gcc-sdm845.c
> +++ b/drivers/clk/qcom/gcc-sdm845.c
> @@ -3169,6 +3169,32 @@ enum {
> },
> };
>
> +static struct clk_branch gcc_lpass_q6_axi_clk = {
> + .halt_reg = 0x47000,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x47000,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_lpass_q6_axi_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_lpass_sway_clk = {
> + .halt_reg = 0x47008,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x47008,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_lpass_sway_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> static struct gdsc pcie_0_gdsc = {
> .gdscr = 0x6b004,
> .pd = {
> @@ -3469,6 +3495,8 @@ enum {
> [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
> [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
> [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
> + [GCC_LPASS_Q6_AXI_CLK] = NULL,
> + [GCC_LPASS_SWAY_CLK] = NULL,
> };
>
> static const struct qcom_reset_map gcc_sdm845_resets[] = {
> @@ -3583,6 +3611,13 @@ static int gcc_sdm845_probe(struct platform_device *pdev)
> if (ret)
> return ret;
>
> + if (!of_property_read_bool(pdev->dev.of_node, "qcom,lpass-protected")) {
> + gcc_sdm845_clocks[GCC_LPASS_Q6_AXI_CLK] =
> + &gcc_lpass_q6_axi_clk.clkr;
> + gcc_sdm845_clocks[GCC_LPASS_SWAY_CLK] =
> + &gcc_lpass_sway_clk.clkr;
> + }
> +
> return qcom_cc_really_probe(pdev, &gcc_sdm845_desc, regmap);
> }
>
> diff --git a/drivers/clk/qcom/lpasscc-sdm845.c b/drivers/clk/qcom/lpasscc-sdm845.c
> new file mode 100644
> index 0000000..f7b9b0f
> --- /dev/null
> +++ b/drivers/clk/qcom/lpasscc-sdm845.c
> @@ -0,0 +1,201 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/bitops.h>
Is this needed?
> +/* CLK_OFF would not toggle until LPASS is not out of reset */
> +static struct clk_branch lpass_qdsp6ss_xo_clk = {
> + .halt_reg = 0x38,
> + .halt_check = BRANCH_HALT_SKIP,
> + .clkr = {
> + .enable_reg = 0x38,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "lpass_qdsp6ss_xo_clk",
> + .flags = CLK_IGNORE_UNUSED,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +/* CLK_OFF would not toggle until LPASS is not out of reset */
Move this comment next to BRANCH_HALT_SKIP please so we know what it
relates to.
> +static struct clk_branch lpass_qdsp6ss_sleep_clk = {
> + .halt_reg = 0x3c,
> + .halt_check = BRANCH_HALT_SKIP,
> + .clkr = {
> + .enable_reg = 0x3c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "lpass_qdsp6ss_sleep_clk",
> + .flags = CLK_IGNORE_UNUSED,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static int lpass_clocks_sdm845_probe(struct platform_device *pdev, int index,
> + const struct qcom_cc_desc *desc)
> +{
> + struct regmap *regmap;
> + struct resource *res;
> + void __iomem *base;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, index);
> + base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + regmap = devm_regmap_init_mmio(&pdev->dev, base, desc->config);
> + if (IS_ERR(regmap))
> + return PTR_ERR(regmap);
If this happens again in the future we should move this into the
common.c file and let qcom_cc_probe_index() exist.
> +
> + return qcom_cc_really_probe(pdev, desc, regmap);
> +}
> +
> +/* LPASS CC clock controller */
Please remove this comment. It's useless.
> +static const struct of_device_id lpass_cc_sdm845_match_table[] = {
> + { .compatible = "qcom,sdm845-lpasscc" },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, lpass_cc_sdm845_match_table);
> +
Powered by blists - more mailing lists