linux-kernel - [PATCH 1/4] MIPS: Define MMIO ordering barriers

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Message-ID: <alpine.LFD.2.21.1810070232470.7757@eddie.linux-mips.org>
Date:   Mon, 8 Oct 2018 01:37:01 +0100 (BST)
From:   "Maciej W. Rozycki" <macro@...ux-mips.org>
To:     Ralf Baechle <ralf@...ux-mips.org>,
        Paul Burton <paul.burton@...s.com>
cc:     linux-mips@...ux-mips.org, linux-kernel@...r.kernel.org
Subject: [PATCH 1/4] MIPS: Define MMIO ordering barriers

Define MMIO ordering barriers as separate operations so as to allow 
making places where such a barrier is required distinct from places 
where a memory or a DMA barrier is needed.

Architecturally MIPS does not specify ordering requirements for uncached 
bus accesses such as MMIO operations normally use and therefore explicit 
barriers have to be inserted between MMIO accesses where unspecified 
ordering of operations would cause unpredictable results.

MIPS MMIO ordering barriers are implemented using the same underlying 
mechanism that memory or a DMA barrier ordering barriers use, that is 
either a suitable SYNC instruction or a platform-specific `wbflush' 
call.  However platforms may implement different ordering rules for 
different kinds of bus activity, so having a separate API makes it 
possible to remove unnecessary barriers and avoid a performance hit they 
may cause due to unrelated bus activity by making their implementation 
expand to nil while keeping the necessary ones.

Also having distinct barriers for each kind of use makes it easier for 
the reader to understand what code has been intended to do.

Signed-off-by: Maciej W. Rozycki <macro@...ux-mips.org>
---
 arch/mips/include/asm/io.h |   12 ++++++++++++
 1 file changed, 12 insertions(+)

linux-mips-iobarrier.patch
Index: linux-20180930-3maxp/arch/mips/include/asm/io.h
===================================================================
--- linux-20180930-3maxp.orig/arch/mips/include/asm/io.h
+++ linux-20180930-3maxp/arch/mips/include/asm/io.h
@@ -20,6 +20,7 @@
 #include <linux/irqflags.h>

 #include <asm/addrspace.h>
+#include <asm/barrier.h>
 #include <asm/bug.h>
 #include <asm/byteorder.h>
 #include <asm/cpu.h>
@@ -80,6 +81,17 @@ static inline void set_io_port_base(unsi
 }

 /*
+ * Enforce in-order execution of data I/O.  In the MIPS architecture
+ * these are equivalent to corresponding platform-specific memory
+ * barriers defined in <asm/barrier.h>.  API pinched from PowerPC,
+ * with sync additionally defined.
+ */
+#define iobarrier_rw() mb()
+#define iobarrier_r() rmb()
+#define iobarrier_w() wmb()
+#define iobarrier_sync() iob()
+
+/*
  * Thanks to James van Artsdalen for a better timing-fix than
  * the two short jumps: using outb's to a nonexistent port seems
  * to guarantee better timings even on fast machines.