linux-kernel - RE: [PATCH 4.18 222/235] drm/amd/pp: Send khz clock values to DC for smu7/8

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Date:   Mon, 8 Oct 2018 14:33:56 +0000
From:   "Deucher, Alexander" <Alexander.Deucher@....com>
To:     Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
CC:     "stable@...r.kernel.org" <stable@...r.kernel.org>,
        "Wentland, Harry" <Harry.Wentland@....com>,
        "Zhu, Rex" <Rex.Zhu@....com>,
        Sasha Levin <alexander.levin@...rosoft.com>
Subject: RE: [PATCH 4.18 222/235] drm/amd/pp: Send khz clock values to DC for
 smu7/8

> -----Original Message-----
> From: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
> Sent: Monday, September 24, 2018 7:53 AM
> To: linux-kernel@...r.kernel.org
> Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>;
> stable@...r.kernel.org; Wentland, Harry <Harry.Wentland@....com>;
> Deucher, Alexander <Alexander.Deucher@....com>; Zhu, Rex
> <Rex.Zhu@....com>; Sasha Levin <alexander.levin@...rosoft.com>
> Subject: [PATCH 4.18 222/235] drm/amd/pp: Send khz clock values to DC for
> smu7/8
> 
> 4.18-stable review patch.  If anyone has any objections, please let me know.
> 

This regresses power usage on 4.18.  Please revert.
https://bugzilla.kernel.org/show_bug.cgi?id=201275

Thanks,

Alex

> ------------------
> 
> From: Harry Wentland <harry.wentland@....com>
> 
> [ Upstream commit c3cb424a086921f6bb0449b10d998352a756d6d5 ]
> 
> The previous change wasn't covering smu 7 and 8 and therefore DC was
> seeing wrong clock values.
> 
> This fixes an issue where the pipes seem to hang with a 4k DP and 1080p
> HDMI display.
> 
> Fixes: c3df50abc84b ("drm/amd/pp: Convert clock unit to KHz as defined")
> Signed-off-by: Harry Wentland <harry.wentland@....com>
> Acked-by: Alex Deucher <alexander.deucher@....com>
> Cc:rex.zhu@....com
> Signed-off-by: Alex Deucher <alexander.deucher@....com>
> Signed-off-by: Sasha Levin <alexander.levin@...rosoft.com>
> Signed-off-by: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c |    8 ++++----
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c |    6 +++---
>  2 files changed, 7 insertions(+), 7 deletions(-)
> 
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -4555,12 +4555,12 @@ static int smu7_get_sclks(struct pp_hwmg
>  			return -EINVAL;
>  		dep_sclk_table = table_info->vdd_dep_on_sclk;
>  		for (i = 0; i < dep_sclk_table->count; i++)
> -			clocks->clock[i] = dep_sclk_table->entries[i].clk;
> +			clocks->clock[i] = dep_sclk_table->entries[i].clk * 10;
>  		clocks->count = dep_sclk_table->count;
>  	} else if (hwmgr->pp_table_version == PP_TABLE_V0) {
>  		sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk;
>  		for (i = 0; i < sclk_table->count; i++)
> -			clocks->clock[i] = sclk_table->entries[i].clk;
> +			clocks->clock[i] = sclk_table->entries[i].clk * 10;
>  		clocks->count = sclk_table->count;
>  	}
> 
> @@ -4592,7 +4592,7 @@ static int smu7_get_mclks(struct pp_hwmg
>  			return -EINVAL;
>  		dep_mclk_table = table_info->vdd_dep_on_mclk;
>  		for (i = 0; i < dep_mclk_table->count; i++) {
> -			clocks->clock[i] = dep_mclk_table->entries[i].clk;
> +			clocks->clock[i] = dep_mclk_table->entries[i].clk * 10;
>  			clocks->latency[i] = smu7_get_mem_latency(hwmgr,
>  						dep_mclk_table-
> >entries[i].clk);
>  		}
> @@ -4600,7 +4600,7 @@ static int smu7_get_mclks(struct pp_hwmg
>  	} else if (hwmgr->pp_table_version == PP_TABLE_V0) {
>  		mclk_table = hwmgr-
> >dyn_state.vddc_dependency_on_mclk;
>  		for (i = 0; i < mclk_table->count; i++)
> -			clocks->clock[i] = mclk_table->entries[i].clk;
> +			clocks->clock[i] = mclk_table->entries[i].clk * 10;
>  		clocks->count = mclk_table->count;
>  	}
>  	return 0;
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c
> @@ -1605,17 +1605,17 @@ static int smu8_get_clock_by_type(struct
>  	switch (type) {
>  	case amd_pp_disp_clock:
>  		for (i = 0; i < clocks->count; i++)
> -			clocks->clock[i] = data->sys_info.display_clock[i];
> +			clocks->clock[i] = data->sys_info.display_clock[i] * 10;
>  		break;
>  	case amd_pp_sys_clock:
>  		table = hwmgr->dyn_state.vddc_dependency_on_sclk;
>  		for (i = 0; i < clocks->count; i++)
> -			clocks->clock[i] = table->entries[i].clk;
> +			clocks->clock[i] = table->entries[i].clk * 10;
>  		break;
>  	case amd_pp_mem_clock:
>  		clocks->count = SMU8_NUM_NBPMEMORYCLOCK;
>  		for (i = 0; i < clocks->count; i++)
> -			clocks->clock[i] = data-
> >sys_info.nbp_memory_clock[clocks->count - 1 - i];
> +			clocks->clock[i] = data-
> >sys_info.nbp_memory_clock[clocks->count - 1
> +- i] * 10;
>  		break;
>  	default:
>  		return -1;
>