linux-kernel - [PATCH v2 0/3] arm64: cpufeature: Fix handling of CTR

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <20181009134707.3479-2-suzuki.poulose@arm.com>
Date:   Tue,  9 Oct 2018 14:47:04 +0100
From:   Suzuki K Poulose <suzuki.poulose@....com>
To:     linux-arm-kernel@...ts.infradead.org
Cc:     linux-kernel@...r.kernel.org, catalin.marinas@....com,
        will.deacon@....com, mark.rutland@....com, pelcan@...eaurora.org,
        shankerd@...eaurora.org, suzuki.poulose@....com
Subject: [PATCH v2 0/3] arm64: cpufeature: Fix handling of CTR_EL0

This series makes sure that we handle the CTR_EL0 field mismatches
properly, especially for the IDC field. Also, skip trapping CTR
accesses on a CPU if it matches the safe value.

Applies on arm64 for-next/core.

Changes since v1
 - Fix wrong hunk in has_cache_idc()
 - Allow a late secondary CPU with raw CTR_EL0.IDC = 0 and effective
   CTR_EL0.IDC = 1, to boot on a system without IDC available.

Suzuki K Poulose (3):
  arm64: cpufeature: ctr: Fix cpu capability check for late CPUs
  arm64: cpufeature: Fix handling of CTR_EL0.IDC field
  arm64: cpufeature: Trap CTR_EL0 access only where it is necessary

 arch/arm64/include/asm/cache.h | 40 ++++++++++++++++++++++++++++++++++
 arch/arm64/kernel/cpu_errata.c | 34 +++++++++++++++++++++++++----
 arch/arm64/kernel/cpufeature.c | 35 +++++++++++++++++++++++++----
 arch/arm64/kernel/cpuinfo.c    | 10 ++++++++-
 4 files changed, 110 insertions(+), 9 deletions(-)

-- 
2.19.0