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Message-Id: <20181016072209.1011-2-mgautam@codeaurora.org>
Date: Tue, 16 Oct 2018 12:52:07 +0530
From: Manu Gautam <mgautam@...eaurora.org>
To: Kishon Vijay Abraham I <kishon@...com>
Cc: linux-arm-msm@...r.kernel.org,
Manu Gautam <mgautam@...eaurora.org>,
Vivek Gautam <vivek.gautam@...eaurora.org>,
Douglas Anderson <dianders@...omium.org>,
Evan Green <evgreen@...omium.org>,
linux-kernel@...r.kernel.org (open list:GENERIC PHY FRAMEWORK)
Subject: [PATCH v2 2/2] phy: qcom-qusb2: Fix HSTX_TRIM tuning with fused value for SDM845
Tune1 register on sdm845 is used to update HSTX_TRIM with fused
setting. Enable same by specifying update_tune1_with_efuse flag
for sdm845, otherwise driver ends up programming tune2 register.
Fixes: ef17f6e212ca ("phy: qcom-qusb2: Add QUSB2 PHYs support for sdm845")
Signed-off-by: Manu Gautam <mgautam@...eaurora.org>
Reviewed-by: Douglas Anderson <dianders@...omium.org>
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
index 9d6c88064158..69c92843eb3b 100644
--- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
+++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
@@ -231,6 +231,7 @@ static const struct qusb2_phy_cfg sdm845_phy_cfg = {
.mask_core_ready = CORE_READY_STATUS,
.has_pll_override = true,
.autoresume_en = BIT(0),
+ .update_tune1_with_efuse = true,
};
static const char * const qusb2_phy_vreg_names[] = {
--
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a Linux Foundation Collaborative Project
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