linux-kernel - [PATCH v9 6/9] PCI: mediatek: Fixup enable MSI logic by enable MSI after clock enabled

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Message-ID: <1539686690-24068-7-git-send-email-honghui.zhang@mediatek.com>
Date:   Tue, 16 Oct 2018 18:44:47 +0800
From:   <honghui.zhang@...iatek.com>
To:     <lorenzo.pieralisi@....com>, <bhelgaas@...gle.com>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-mediatek@...ts.infradead.org>, <linux-pci@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <ryder.lee@...iatek.com>
CC:     <ulf.hansson@...aro.org>, <marc.zyngier@....com>,
        <matthias.bgg@...il.com>, <devicetree@...r.kernel.org>,
        <yingjoe.chen@...iatek.com>, <eddie.huang@...iatek.com>,
        <honghui.zhang@...iatek.com>, <youlin.pei@...iatek.com>,
        <yt.shen@...iatek.com>, <jianjun.wang@...iatek.com>
Subject: [PATCH v9 6/9] PCI: mediatek: Fixup enable MSI logic by enable MSI after clock enabled

From: Honghui Zhang <honghui.zhang@...iatek.com>

The commit 43e6409db64d ("PCI: mediatek: Add MSI support for MT2712 and
MT7622") added MSI support but enable MSI in wrong place, clocks was not
enabled when enable MSI. This patch fix this issue by calling
mtk_pcie_enable_msi in mtk_pcie_startup_port_v2 since the clock was all
enabled at that time.

Fixes: 43e6409db64d ("PCI: mediatek: Add MSI support for MT2712 and MT7622")
Signed-off-by: Honghui Zhang <honghui.zhang@...iatek.com>
Acked-by: Ryder Lee <ryder.lee@...iatek.com>
---
 drivers/pci/controller/pcie-mediatek.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
index 6967bb7..82d3d85 100644
--- a/drivers/pci/controller/pcie-mediatek.c
+++ b/drivers/pci/controller/pcie-mediatek.c
@@ -568,8 +568,6 @@ static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port,
 		ret = mtk_pcie_allocate_msi_domains(port);
 		if (ret)
 			return ret;
-
-		mtk_pcie_enable_msi(port);
 	}
 
 	return 0;
@@ -690,6 +688,9 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
 	val &= ~INTX_MASK;
 	writel(val, port->base + PCIE_INT_MASK);
 
+	if (IS_ENABLED(CONFIG_PCI_MSI))
+		mtk_pcie_enable_msi(port);
+
 	/* Set AHB to PCIe translation windows */
 	size = mem->end - mem->start;
 	val = lower_32_bits(mem->start) | AHB2PCIE_SIZE(fls(size));
-- 
2.6.4