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Message-ID: <CAK8P3a1ME=1Gb1d_q_+9zP4bLr9wJC7hmEv4KGCt5GN6dG5F8g@mail.gmail.com>
Date: Wed, 17 Oct 2018 17:06:56 +0200
From: Arnd Bergmann <arnd@...db.de>
To: Guo Ren <ren_guo@...ky.com>
Cc: Andrew Morton <akpm@...ux-foundation.org>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
David Miller <davem@...emloft.net>,
gregkh <gregkh@...uxfoundation.org>,
Christoph Hellwig <hch@...radead.org>,
Marc Zyngier <marc.zyngier@....com>,
Mark Rutland <mark.rutland@....com>,
Peter Zijlstra <peterz@...radead.org>,
Rob Herring <robh@...nel.org>,
Thomas Gleixner <tglx@...utronix.de>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
linux-arch <linux-arch@...r.kernel.org>,
DTML <devicetree@...r.kernel.org>,
Rob Herring <robh+dt@...nel.org>, c-sky_gcc_upstream@...ky.com
Subject: Re: [PATCH V9 07/21] csky: MMU and page table management
On Tue, Oct 16, 2018 at 5:01 AM Guo Ren <ren_guo@...ky.com> wrote:
>
> This patch adds files related to memory management and here is our
> memory-layout:
>
> Fixmap : 0xffc02000 – 0xfffff000 (4 MB - 12KB)
> Pkmap : 0xff800000 – 0xffc00000 (4 MB)
> Vmalloc : 0xf0200000 – 0xff000000 (238 MB)
> Lowmem : 0x80000000 – 0xc0000000 (1GB)
>
> abiv1 CPU (CK610) is VIPT cache and it doesn't support highmem.
> abiv2 CPUs are all PIPT cache and they could support highmem.
>
> Lowmem is directly mapped by msa0 & msa1 reg, and we needn't setup
> memory page table for it.
>
> Link:https://lore.kernel.org/lkml/20180518215548.GH17671@n2100.armlinux.org.uk/
> Signed-off-by: Guo Ren <ren_guo@...ky.com>
> Cc: Christoph Hellwig <hch@...radead.org>
> Cc: Arnd Bergmann <arnd@...db.de>
Reviewed-by: Arnd Bergmann <arnd@...db.de>
Christoph had all the useful comments on this one, I just checked that I didn't
spot anything beyond that.
Arnd
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