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Message-ID: <20181018204801.GA2009@bogus>
Date: Thu, 18 Oct 2018 15:48:01 -0500
From: Rob Herring <robh@...nel.org>
To: Robin Murphy <robin.murphy@....com>
Cc: hannah@...vell.com, catalin.marinas@....com, will.deacon@....com,
corbet@....net, joro@...tes.org, gregory.clement@...tlin.com,
mark.rutland@....com, jason@...edaemon.net, andrew@...n.ch,
sebastian.hesselbarth@...il.com, devicetree@...r.kernel.org,
linux-doc@...r.kernel.org, omrii@...vell.com,
linux-kernel@...r.kernel.org, nadavh@...vell.com,
iommu@...ts.linux-foundation.org, thomas.petazzoni@...tlin.com,
linux-arm-kernel@...ts.infradead.org, nd@....com
Subject: Re: [PATCH 3/4] dt-bindings: iommu/arm, smmu: add compatible string
for Marvell
On Mon, Oct 15, 2018 at 02:11:52PM +0100, Robin Murphy wrote:
> On 15/10/18 13:00, hannah@...vell.com wrote:
> > From: Hanna Hawa <hannah@...vell.com>
> >
> > Add specific compatible string for Marvell usage due errata of
> > accessing 64bit registers of ARM SMMU, in AP806.
> >
> > AP806 SOC use the generic ARM-MMU500, and there's no specific
> > implementation of Marvell, this compatible is used for errata only.
>
> Given that, I think something more specific like:
>
> "marvell,ap806-smmu", "arm,mmu-500";
>
> would be most appropriate. Otherwise, if some future Marvell SoC were to
> ever come out with a *different* MMU-500 integration problem, you'd already
> have painted yourself into a corner.
>
> Alternatively (or additionally), we could perhaps consider a separate
> property like "marvell,32bit-config-access", to mirror the existing handling
> of the secure integration bug.
The former please. We have learned our lesson there (though for some
reason, that was the *only* SMMU problem in Calxeda Midway ;) ).
Rob
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