linux-kernel - Re: [PATCH 3/4] irqchip/mbigen: add support for a MBIGEN generating SPIs

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Message-ID: <fde290c2-01e3-d5a8-eaa9-e7faaabf84ec@huawei.com>
Date:   Thu, 18 Oct 2018 20:54:40 +0800
From:   Hanjun Guo <guohanjun@...wei.com>
To:     Marc Zyngier <marc.zyngier@....com>,
        Yang Yingliang <yangyingliang@...wei.com>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>
CC:     <tglx@...utronix.de>
Subject: Re: [PATCH 3/4] irqchip/mbigen: add support for a MBIGEN generating
 SPIs

On 2018/10/18 19:56, Marc Zyngier wrote:
> Hi Hanjun,
> 
> On 18/10/18 12:20, Hanjun Guo wrote:
>> Hi Marc,
>>
>>>>>>
>>>>> Now, the biggest question of them all: how does it work with ACPI? Last
>>>>> time I checked, there was no DT support for platforms using the MBIGEN.
>>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/hisilicon/hip07.dtsi
>>>> This DT describes how platform devices using the MBIGEN.
>>>
>>> That's not how my own D05 boots. It is ACPI only. How is that going to
>>> work on this platform?
>>
>> D05 is ACPI only so it has no dtb in the firmware, that's why we can
>> boot D05 without acpi=on in the boot cmdline, but if you want to
>> boot D05 with dtb, you could try to specify the dtb in the grub
>> (seems centos based):
>>
>> menuentry "example" --id example{
>>         linux /Image-kernel root=... rdinit=...
>>         initrd /example.img
>>         devicetree /d05.dtb
>> }
> 
> Sure. But what I'm asking here is how this change in the MBIGEN driver
> can be beneficial to people who need ACPI, for better or worse? For
> example, you cannot get the PCIe SMMU without ACPI. Good-bye VFIO.
> 
> If it is DT only, I seriously doubt anyone will be able to use it.

We have another ARM64 SoC for wireless base station which with the
same CPU DIE but different IO DIE, they share the same mbigen controller.

Since we use big-endian on wireless base station so only DT is available
(EFI stub is little-endian), we need to reuse this mbigen driver
on this SoC (not the one for D05) as well, not sure if this makes sense
to you, please let us know.

Thanks
Hanjun