lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Fri, 19 Oct 2018 09:47:01 +0000
From:   Naga Sureshkumar Relli <nagasure@...inx.com>
To:     Boris Brezillon <boris.brezillon@...tlin.com>
CC:     "miquel.raynal@...tlin.com" <miquel.raynal@...tlin.com>,
        "richard@....at" <richard@....at>,
        "dwmw2@...radead.org" <dwmw2@...radead.org>,
        "computersforpeace@...il.com" <computersforpeace@...il.com>,
        "marek.vasut@...il.com" <marek.vasut@...il.com>,
        Michal Simek <michals@...inx.com>,
        "linux-mtd@...ts.infradead.org" <linux-mtd@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "nagasuresh12@...il.com" <nagasuresh12@...il.com>
Subject: RE: [LINUX PATCH v11 3/3] mtd: rawnand: arasan: Add support for
 Arasan NAND Flash Controller

Hi Boris,

> -----Original Message-----
> From: Boris Brezillon [mailto:boris.brezillon@...tlin.com]
> Sent: Thursday, October 4, 2018 1:17 AM
> To: Naga Sureshkumar Relli <nagasure@...inx.com>
> Cc: miquel.raynal@...tlin.com; richard@....at; dwmw2@...radead.org;
> computersforpeace@...il.com; marek.vasut@...il.com; Michal Simek
> <michals@...inx.com>; linux-mtd@...ts.infradead.org; linux-kernel@...r.kernel.org;
> nagasuresh12@...il.com
> Subject: Re: [LINUX PATCH v11 3/3] mtd: rawnand: arasan: Add support for Arasan
> NAND Flash Controller
> 
> On Tue, 25 Sep 2018 17:50:31 +0530
> Naga Sureshkumar Relli <naga.sureshkumar.relli@...inx.com> wrote:
> 
> > +static int anfc_zero_len_page_write_type_exec(struct nand_chip *chip,
> > +					      const struct nand_subop *subop) {
> > +	const struct nand_op_instr *instr;
> > +	struct anfc_nand_chip *achip = to_anfc_nand(chip);
> > +	struct anfc_nand_controller *nfc = to_anfc(chip->controller);
> > +	unsigned int op_id;
> > +	struct anfc_op nfc_op = {};
> > +	struct mtd_info *mtd = nand_to_mtd(chip);
> > +	u32 addrcycles;
> > +
> > +	anfc_parse_instructions(chip, subop, &nfc_op);
> > +	nfc->prog = PROG_PGRD;
> > +	instr = nfc_op.data_instr;
> > +	op_id = nfc_op.data_instr_idx;
> > +
> > +	addrcycles = achip->raddr_cycles + achip->caddr_cycles;
> > +
> > +	anfc_prepare_cmd(nfc, nfc_op.cmds[0], NAND_CMD_PAGEPROG, 1,
> 
> Why are the second opcode and the number of address cycles hardcoded.
> That's simply not future-proof, and I don't want that. Also, I don't understand why you do
> that, you have all the information you need in subop and you keep guessing some parameters.
Ok, I will remove all these hard coding commands from the driver, instead I will use nfc_op.cmds[0], nfc_op.cmds[1].

Thanks,
Naga Sureshkumar Relli
> 
> > +			 mtd->writesize, addrcycles);
> > +	anfc_setpagecoladdr(nfc, nfc_op.row, nfc_op.col);
> > +
> > +	return 0;
> > +}

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ