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Message-ID: <201810191212.SupLdsPZ%fengguang.wu@intel.com>
Date: Fri, 19 Oct 2018 12:44:40 +0800
From: kbuild test robot <lkp@...el.com>
To: Stefan Popa <stefan.popa@...log.com>
Cc: kbuild-all@...org, jic23@...nel.org, Michael.Hennerich@...log.com,
knaack.h@....de, lars@...afoo.de, pmeerw@...erw.net,
gregkh@...uxfoundation.org, linux-kernel@...r.kernel.org,
linux-iio@...r.kernel.org, stefan.popa@...log.com
Subject: Re: [PATCH 1/2] iio: adc: Add ad7124 support
Hi Stefan,
I love your patch! Yet something to improve:
[auto build test ERROR on iio/togreg]
[also build test ERROR on v4.19-rc8 next-20181018]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Stefan-Popa/iio-adc-Add-ad7124-support/20181019-051737
base: https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio.git togreg
config: arm-allmodconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=7.2.0 make.cross ARCH=arm
All error/warnings (new ones prefixed by >>):
>> drivers/iio//adc/ad7124.c:215:3: error: 'const struct ad_sigma_delta_info' has no member named 'data_reg'
.data_reg = AD7124_DATA,
^~~~~~~~
>> drivers/iio//adc/ad7124.c:25:23: warning: excess elements in struct initializer
#define AD7124_DATA 0x02
^
>> drivers/iio//adc/ad7124.c:215:14: note: in expansion of macro 'AD7124_DATA'
.data_reg = AD7124_DATA,
^~~~~~~~~~~
drivers/iio//adc/ad7124.c:25:23: note: (near initialization for 'ad7124_sigma_delta_info')
#define AD7124_DATA 0x02
^
>> drivers/iio//adc/ad7124.c:215:14: note: in expansion of macro 'AD7124_DATA'
.data_reg = AD7124_DATA,
^~~~~~~~~~~
vim +215 drivers/iio//adc/ad7124.c
20
21 /* AD7124 registers */
22 #define AD7124_COMMS 0x00
23 #define AD7124_STATUS 0x00
24 #define AD7124_ADC_CONTROL 0x01
> 25 #define AD7124_DATA 0x02
26 #define AD7124_IO_CONTROL_1 0x03
27 #define AD7124_IO_CONTROL_2 0x04
28 #define AD7124_ID 0x05
29 #define AD7124_ERROR 0x06
30 #define AD7124_ERROR_EN 0x07
31 #define AD7124_MCLK_COUNT 0x08
32 #define AD7124_CHANNEL(x) (0x09 + (x))
33 #define AD7124_CONFIG(x) (0x19 + (x))
34 #define AD7124_FILTER(x) (0x21 + (x))
35 #define AD7124_OFFSET(x) (0x29 + (x))
36 #define AD7124_GAIN(x) (0x31 + (x))
37
38 /* AD7124_STATUS */
39 #define AD7124_STATUS_POR_FLAG_MSK BIT(4)
40
41 /* AD7124_ADC_CONTROL */
42 #define AD7124_ADC_CTRL_PWR_MSK GENMASK(7, 6)
43 #define AD7124_ADC_CTRL_PWR(x) FIELD_PREP(AD7124_ADC_CTRL_PWR_MSK, x)
44 #define AD7124_ADC_CTRL_MODE_MSK GENMASK(5, 2)
45 #define AD7124_ADC_CTRL_MODE(x) FIELD_PREP(AD7124_ADC_CTRL_MODE_MSK, x)
46
47 /* AD7124_CHANNEL_X */
48 #define AD7124_CHANNEL_EN_MSK BIT(15)
49 #define AD7124_CHANNEL_EN(x) FIELD_PREP(AD7124_CHANNEL_EN_MSK, x)
50 #define AD7124_CHANNEL_SETUP_MSK GENMASK(14, 12)
51 #define AD7124_CHANNEL_SETUP(x) FIELD_PREP(AD7124_CHANNEL_SETUP_MSK, x)
52 #define AD7124_CHANNEL_AINP_MSK GENMASK(9, 5)
53 #define AD7124_CHANNEL_AINP(x) FIELD_PREP(AD7124_CHANNEL_AINP_MSK, x)
54 #define AD7124_CHANNEL_AINM_MSK GENMASK(4, 0)
55 #define AD7124_CHANNEL_AINM(x) FIELD_PREP(AD7124_CHANNEL_AINM_MSK, x)
56
57 /* AD7124_CONFIG_X */
58 #define AD7124_CONFIG_BIPOLAR_MSK BIT(11)
59 #define AD7124_CONFIG_BIPOLAR(x) FIELD_PREP(AD7124_CONFIG_BIPOLAR_MSK, x)
60 #define AD7124_CONFIG_REF_SEL_MSK GENMASK(4, 3)
61 #define AD7124_CONFIG_REF_SEL(x) FIELD_PREP(AD7124_CONFIG_REF_SEL_MSK, x)
62 #define AD7124_CONFIG_PGA_MSK GENMASK(2, 0)
63 #define AD7124_CONFIG_PGA(x) FIELD_PREP(AD7124_CONFIG_PGA_MSK, x)
64
65 /* AD7124_FILTER_X */
66 #define AD7124_FILTER_FS_MSK GENMASK(10, 0)
67 #define AD7124_FILTER_FS(x) FIELD_PREP(AD7124_FILTER_FS_MSK, x)
68
69 enum ad7124_ids {
70 ID_AD7124_4,
71 ID_AD7124_8,
72 };
73
74 enum ad7124_ref_sel {
75 AD7124_REFIN1,
76 AD7124_REFIN2,
77 AD7124_INT_REF,
78 AD7124_AVDD_REF,
79 };
80
81 enum ad7124_power_mode {
82 AD7124_LOW_POWER,
83 AD7124_MID_POWER,
84 AD7124_FULL_POWER,
85 };
86
87 static const unsigned int ad7124_gain[8] = {
88 1, 2, 4, 8, 16, 32, 64, 128
89 };
90
91 static const int ad7124_master_clk_freq_hz[3] = {
92 [AD7124_LOW_POWER] = 76800,
93 [AD7124_MID_POWER] = 153600,
94 [AD7124_FULL_POWER] = 614400,
95 };
96
97 static const char * const ad7124_ref_names[] = {
98 [AD7124_REFIN1] = "refin1",
99 [AD7124_REFIN2] = "refin2",
100 [AD7124_INT_REF] = "int",
101 [AD7124_AVDD_REF] = "avdd",
102 };
103
104 struct ad7124_chip_info {
105 unsigned int num_inputs;
106 };
107
108 struct ad7124_channel_config {
109 enum ad7124_ref_sel refsel;
110 bool bipolar;
111 unsigned int ain;
112 unsigned int vref_mv;
113 unsigned int pga_bits;
114 unsigned int odr;
115 };
116
117 struct ad7124_state {
118 const struct ad7124_chip_info *chip_info;
119 struct ad_sigma_delta sd;
120 struct ad7124_channel_config channel_config[4];
121 struct regulator *vref[4];
122 struct clk *mclk;
123 unsigned int adc_control;
124 unsigned int num_channels;
125 };
126
127 static const struct iio_chan_spec ad7124_channel_template = {
128 .type = IIO_VOLTAGE,
129 .indexed = 1,
130 .differential = 1,
131 .channel = 0,
132 .address = 0,
133 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
134 BIT(IIO_CHAN_INFO_SCALE) |
135 BIT(IIO_CHAN_INFO_OFFSET) |
136 BIT(IIO_CHAN_INFO_SAMP_FREQ),
137 .scan_index = 0,
138 .scan_type = {
139 .sign = 'u',
140 .realbits = 24,
141 .storagebits = 32,
142 .shift = 0,
143 },
144 };
145
146 static struct ad7124_chip_info ad7124_chip_info_tbl[] = {
147 [ID_AD7124_4] = {
148 .num_inputs = 8,
149 },
150 [ID_AD7124_8] = {
151 .num_inputs = 16,
152 },
153 };
154
155 static int ad7124_find_closest_match(const int *array,
156 unsigned int size, int val)
157 {
158 int i;
159
160 for (i = 0; i < size; i++) {
161 if (val <= array[i])
162 return i;
163 }
164
165 return size - 1;
166 }
167
168 static int ad7124_spi_write_mask(struct ad7124_state *st,
169 unsigned int addr,
170 unsigned long mask,
171 unsigned int val,
172 unsigned int bytes)
173 {
174 unsigned int readval;
175 int ret;
176
177 ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval);
178 if (ret < 0)
179 return ret;
180
181 readval &= ~mask;
182 readval |= val;
183
184 return ad_sd_write_reg(&st->sd, addr, bytes, readval);
185 }
186
187 static int ad7124_set_mode(struct ad_sigma_delta *sd,
188 enum ad_sigma_delta_mode mode)
189 {
190 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
191
192 st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK;
193 st->adc_control |= AD7124_ADC_CTRL_MODE(mode);
194
195 return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
196 }
197
198 static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
199 {
200 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
201 unsigned int val;
202
203 val = st->channel_config[channel].ain | AD7124_CHANNEL_EN(1) |
204 AD7124_CHANNEL_SETUP(channel);
205
206 return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(channel), 2, val);
207 }
208
209 static const struct ad_sigma_delta_info ad7124_sigma_delta_info = {
210 .set_channel = ad7124_set_channel,
211 .set_mode = ad7124_set_mode,
212 .has_registers = true,
213 .addr_shift = 0,
214 .read_mask = BIT(6),
> 215 .data_reg = AD7124_DATA,
216 };
217
---
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