linux-kernel - [PATCH 4/4] pvpanic: add document for pvpanic-mmio DT

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Date:   Wed, 24 Oct 2018 01:25:37 +0800
From:   Peng Hao <peng.hao2@....com.cn>
To:     robh+dt@...nel.org, mark.rutland@....com, arnd@...db.de,
        gregkh@...uxfoundation.org, andy@...radead.org,
        dvhart@...radead.org
Cc:     linux-kernel@...r.kernel.org, platform-driver-x86@...r.kernel.org,
        hutao@...fujitsu.com, Peng Hao <peng.hao2@....com.cn>
Subject: [PATCH 4/4]  pvpanic: add document for pvpanic-mmio DT

Signed-off-by: Peng Hao <peng.hao2@....com.cn>
---
 .../devicetree/bindings/arm/pvpanic-mmio.txt       | 26 ++++++++++++++++++++++
 1 file changed, 26 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/pvpanic-mmio.txt

diff --git a/Documentation/devicetree/bindings/arm/pvpanic-mmio.txt b/Documentation/devicetree/bindings/arm/pvpanic-mmio.txt
new file mode 100644
index 0000000..96c84e15
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/pvpanic-mmio.txt
@@ -0,0 +1,26 @@
+* QEMU PVPANIC MMIO Configuration bindings for ARM
+
+QEMU's aarch64-softmmu emulation / virtualization targets provide the
+following PVPANIC MMIO Configuration interface on the "virt" machine
+type:
+
+- a read-write, 16-bit wide data register.
+
+QEMU exposes the data register to ARM guests as memory mapped registers.
+
+Required properties:
+
+- compatible: "qemu,pvpanic-mmio".
+
+Example:
+
+/ {
+        #size-cells = <0x2>;
+        #address-cells = <0x2>;
+
+        pvpanic-mmio@...0000 {
+                compatible = "qemu,pvpanic-mmio";
+                reg = <0x0 0x9060000 0x0 0x2>;
+        };
+};
+
-- 
1.8.3.1