linux-kernel - Re: CRC errors between mvneta and macb

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Message-ID: <302ebc5c-0c07-dc4e-73ed-6a4adb9cbee4@sorico.fr>
Date:   Tue, 23 Oct 2018 14:37:27 +0200
From:   Richard Genoud <richard.genoud@...il.com>
To:     Andrew Lunn <andrew@...n.ch>
Cc:     Willy Tarreau <w@....eu>, linux-kernel@...r.kernel.org,
        Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
        Antoine Tenart <antoine.tenart@...tlin.com>,
        Gregory CLEMENT <gregory.clement@...tlin.com>,
        Yelena Krivosheev <yelena@...vell.com>,
        Maxime Chevallier <maxime.chevallier@...tlin.com>,
        Nicolas Ferre <nicolas.ferre@...rochip.com>,
        netdev@...r.kernel.org
Subject: Re: CRC errors between mvneta and macb

Le 22/10/2018 à 20:19, Andrew Lunn a écrit :
>> I dug more on the subject, and I think I found what Marvell's PHY/MAC
>> doesn't like.
> 
> Hi Richard
> 
> What PHY is being used?
> 
>> After analyzing the ethernet frame on the Davicom PHY's output (pin
>> TX+), I find out that the FCS errors occurs when the ethernet preamble
>> is longer than 56bits. (something like 58 or 60 bits)
> 
> Some Marvell PHYs have a register bit which might be of interest: Page
> 2, register 16, bit 6.
> 
> 0 = Pad odd nibble preambles in copper receive packets.
> 1 = Pass as is and do not pad odd nibble preambles in
It doesn't seem to change anything.

But the problem really seems to be between the 88E1512 and mvneta.

In mvneta_rx_swbm() I dumped the data received, in both cases, I've got
the same thing:
0000 0000 0000 0000 0004 a3d2 a7ef 0800
dead beef 0000 0000 0000 0000 0000 0000
0000 0000 0000 0000 0000 0000 0000 0000
0000 0000 0000 0000 0000 0000 0000 8a86 ce78
The 2 first bytes are the marvell header, and 4 last the CRC
In one case the MVNETA_RXD_ERR_SUMMARY status bit is set, and not in the
other case.

But I don't have access to the Marvell documentation to know exactly
what is the status "MVNETA_RXD_ERR_CRC".

Richard