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Message-Id: <20181023155035.9101-9-jagan@amarulasolutions.com>
Date: Tue, 23 Oct 2018 21:20:28 +0530
From: Jagan Teki <jagan@...rulasolutions.com>
To: Maxime Ripard <maxime.ripard@...e-electrons.com>,
Chen-Yu Tsai <wens@...e.org>, Icenowy Zheng <icenowy@...c.io>,
Jernej Skrabec <jernej.skrabec@...l.net>,
Vasily Khoruzhick <anarsoul@...il.com>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will.deacon@....com>,
David Airlie <airlied@...ux.ie>,
dri-devel@...ts.freedesktop.org,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, linux-clk@...r.kernel.org,
Michael Trimarchi <michael@...rulasolutions.com>,
linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-sunxi@...glegroups.com
Cc: Jagan Teki <jagan@...rulasolutions.com>
Subject: [PATCH v2 08/15] drm/sun4i: sun6i_mipi_dsi: Fix TCON DRQ set bits
TCON DRQ set bits for non-burst DSI mode can computed via
horizontal front porch instead of front porch + sync timings.
According to BSP code form BPI-M64-bsp in
linux-sunxi/drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c
TCON DRQ set bits are computed for non-burst mode as
=> panel->lcd_ht - panel->lcd_x - panel->lcd_hbp
=> (timmings->hor_front_porch + panel->lcd_hbp + panel->lcd_x)
- panel->lcd_x - panel->hbp
=> timmings->hor_front_porch
=> mode->hsync_start - mode->hdisplay
So, update the DRQ set bits accordingly.
Signed-off-by: Jagan Teki <jagan@...rulasolutions.com>
---
Changes for v2:
- Add detailed commit message
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
index 3a1d48bc1996..8d154cf2e6d6 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
@@ -367,9 +367,9 @@ static void sun6i_dsi_setup_burst(struct sun6i_dsi *dsi,
struct mipi_dsi_device *device = dsi->device;
u32 val = 0;
- if ((mode->hsync_end - mode->hdisplay) > 20) {
+ if ((mode->hsync_start - mode->hdisplay) > 20) {
/* Maaaaaagic */
- u16 drq = (mode->hsync_end - mode->hdisplay) - 20;
+ u16 drq = (mode->hsync_start - mode->hdisplay) - 20;
drq *= mipi_dsi_pixel_format_to_bpp(device->format);
drq /= 32;
--
2.18.0.321.gffc6fa0e3
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