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Message-ID: <154037098047.53599.11415144740017316303@swboyd.mtv.corp.google.com>
Date: Wed, 24 Oct 2018 01:49:40 -0700
From: Stephen Boyd <sboyd@...nel.org>
To: Catalin Marinas <catalin.marinas@....com>,
Chen-Yu Tsai <wens@...e.org>, David Airlie <airlied@...ux.ie>,
Icenowy Zheng <icenowy@...c.io>,
Jagan Teki <jagan@...rulasolutions.com>,
Jernej Skrabec <jernej.skrabec@...l.net>,
Mark Rutland <mark.rutland@....com>,
Maxime Ripard <maxime.ripard@...e-electrons.com>,
Michael Trimarchi <michael@...rulasolutions.com>,
Michael Turquette <mturquette@...libre.com>,
Rob Herring <robh+dt@...nel.org>,
Vasily Khoruzhick <anarsoul@...il.com>,
Will Deacon <will.deacon@....com>, devicetree@...r.kernel.org,
dri-devel@...ts.freedesktop.org,
linux-arm-kernel@...ts.infradead.org, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-sunxi@...glegroups.com
Cc: Jagan Teki <jagan@...rulasolutions.com>
Subject: Re: [PATCH v2 12/15] clk: sunxi-ng: a64: Add min and max rate for PLL_MIPI
Quoting Jagan Teki (2018-10-23 08:50:32)
> A64 manual say PLL_MIPI rates are 500MHz to 1.4GHz, but
> using minimum 500MHz can't release the clock and which
> is not working.
>
> So use working minimum rate as 300MHz which is tested on
> Bananapi DSI panel.
That's weird, but OK.
>
> Signed-off-by: Jagan Teki <jagan@...rulasolutions.com>
> ---
Acked-by: Stephen Boyd <sboyd@...nel.org>
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