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Message-ID: <1e30cef737d040ad4cae7e80737354d370ce938e.1540349544.git.nickhu@andestech.com>
Date: Wed, 24 Oct 2018 11:01:59 +0800
From: Nickhu <nickhu@...estech.com>
To: <greentime@...estech.com>, <linux-kernel@...r.kernel.org>,
<arnd@...db.de>, <robh+dt@...nel.org>, <mark.rutland@....com>,
<deanbo422@...il.com>, <peterz@...radead.org>, <mingo@...hat.com>,
<acme@...nel.org>, <alexander.shishkin@...ux.intel.com>,
<jolsa@...hat.com>, <namhyung@...nel.org>, <ebiederm@...ssion.com>,
<pombredanne@...b.com>, <tglx@...utronix.de>,
<kstewart@...uxfoundation.org>, <gregkh@...uxfoundation.org>,
<john.garry@...wei.com>, <devicetree@...r.kernel.org>,
<zong@...estech.com>, <alankao@...estech.com>
CC: Nickhu <nickhu@...estech.com>, <green.hu@...il.com>
Subject: [PATCH 1/4] nds32: Fix bug in bitfield.h
There two bitfield bug for perfomance counter
in bitfield.h:
PFM_CTL_offSEL1 21 --> 16
PFM_CTL_offSEL2 27 --> 22
This commit fix it.
Signed-off-by: Nickhu <nickhu@...estech.com>
---
arch/nds32/include/asm/bitfield.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/nds32/include/asm/bitfield.h b/arch/nds32/include/asm/bitfield.h
index 8e84fc385b94..19b2841219ad 100644
--- a/arch/nds32/include/asm/bitfield.h
+++ b/arch/nds32/include/asm/bitfield.h
@@ -692,8 +692,8 @@
#define PFM_CTL_offKU1 13 /* Enable user mode event counting for PFMC1 */
#define PFM_CTL_offKU2 14 /* Enable user mode event counting for PFMC2 */
#define PFM_CTL_offSEL0 15 /* The event selection for PFMC0 */
-#define PFM_CTL_offSEL1 21 /* The event selection for PFMC1 */
-#define PFM_CTL_offSEL2 27 /* The event selection for PFMC2 */
+#define PFM_CTL_offSEL1 16 /* The event selection for PFMC1 */
+#define PFM_CTL_offSEL2 22 /* The event selection for PFMC2 */
/* bit 28:31 reserved */
#define PFM_CTL_mskEN0 ( 0x01 << PFM_CTL_offEN0 )
--
2.17.0
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