[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <380d73a8-2e54-3cee-2fdd-c6e891df93f7@ti.com>
Date: Wed, 24 Oct 2018 17:43:00 -0500
From: Grygorii Strashko <grygorii.strashko@...com>
To: Boris Brezillon <boris.brezillon@...tlin.com>
CC: Wolfram Sang <wsa@...-dreams.de>, <linux-i2c@...r.kernel.org>,
Jonathan Corbet <corbet@....net>, <linux-doc@...r.kernel.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Arnd Bergmann <arnd@...db.de>,
Przemyslaw Sroka <psroka@...ence.com>,
Arkadiusz Golec <agolec@...ence.com>,
Alan Douglas <adouglas@...ence.com>,
Bartosz Folta <bfolta@...ence.com>,
Damian Kos <dkos@...ence.com>,
Alicja Jurasik-Urbaniak <alicja@...ence.com>,
Cyprian Wronka <cwronka@...ence.com>,
Suresh Punnoose <sureshp@...ence.com>,
Rafal Ciepiela <rafalc@...ence.com>,
Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
Nishanth Menon <nm@...com>, Rob Herring <robh+dt@...nel.org>,
Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Kumar Gala <galak@...eaurora.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
Vitor Soares <Vitor.Soares@...opsys.com>,
Geert Uytterhoeven <geert@...ux-m68k.org>,
Linus Walleij <linus.walleij@...aro.org>,
Xiang Lin <Xiang.Lin@...aptics.com>,
<linux-gpio@...r.kernel.org>, Sekhar Nori <nsekhar@...com>,
Przemyslaw Gaj <pgaj@...ence.com>,
Peter Rosin <peda@...ntia.se>,
Mike Shettel <mshettel@...eaurora.org>,
Stephen Boyd <swboyd@...omium.org>,
Joe Perches <joe@...ches.com>
Subject: Re: [PATCH v9 6/9] i3c: master: Add driver for Cadence IP
On 10/24/18 4:04 PM, Boris Brezillon wrote:
> On Wed, 24 Oct 2018 15:25:17 -0500
> Grygorii Strashko <grygorii.strashko@...com> wrote:
>
>> On 10/24/18 1:20 PM, Boris Brezillon wrote:
>>> Hi Arnd,
>>>
>>> On Mon, 22 Oct 2018 15:34:01 +0200
>>> Boris Brezillon <boris.brezillon@...tlin.com> wrote:
>>>
>>>
>>>> +
>>>> +static void cdns_i3c_master_rd_from_rx_fifo(struct cdns_i3c_master *master,
>>>> + u8 *bytes, int nbytes)
>>>> +{
>>>> + readsl(master->regs + RX_FIFO, bytes, nbytes / 4);
>>>
>>> Vitor reported a problem with readsl(): this function expects the 2nd
>>> argument to be aligned on 32-bit, which is not guaranteed here. Unless
>>> you see a better solution, I'll switch back to a loop doing:
>>>
>>> for (i = 0; i < nbytes; i += 4) {
>>> u32 tmp = __raw_readl(...);
>>
>> Pls, do not use __raw io.
>
> Except this is exactly what I want here, unless you have a
> replacement for "readl() without a mem-barrier and without endianness
> conversion"
>
Not sure why endianness is the problem. readl_relaxed?
Sry, I've missed that this is part of the driver not i3c core,
so minor/ignore.
--
regards,
-grygorii
Powered by blists - more mailing lists