| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Thu, 25 Oct 2018 19:31:55 +0800
From: kbuild test robot <lkp@...el.com>
To: "Z.q. Hou" <zhiqiang.hou@....com>
Cc: kbuild-all@...org,
"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"bhelgaas@...gle.com" <bhelgaas@...gle.com>,
"lorenzo.pieralisi@....com" <lorenzo.pieralisi@....com>,
"jingoohan1@...il.com" <jingoohan1@...il.com>,
"gustavo.pimentel@...opsys.com" <gustavo.pimentel@...opsys.com>,
Roy Zang <roy.zang@....com>, Mingkai Hu <mingkai.hu@....com>,
"M.h. Lian" <minghuan.lian@....com>,
"Z.q. Hou" <zhiqiang.hou@....com>
Subject: Re: [PATCH 4/4] PCI/dwc: Add more than 4GiB range support
Hi Hou,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on pci/next]
[also build test WARNING on v4.19 next-20181019]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Z-q-Hou/PCI-dwc-Add-more-than-4GiB-range-support/20181025-173802
base: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
config: i386-randconfig-s1-201842 (attached as .config)
compiler: gcc-6 (Debian 6.4.0-9) 6.4.0 20171026
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
All warnings (new ones prefixed by >>):
In file included from include/linux/printk.h:336:0,
from include/linux/kernel.h:14,
from include/linux/list.h:9,
from include/linux/preempt.h:11,
from include/linux/spinlock.h:51,
from include/linux/irq.h:14,
from include/linux/irqchip/chained_irq.h:21,
from drivers/pci/controller/dwc/pcie-designware-host.c:11:
drivers/pci/controller/dwc/pcie-designware-host.c: In function 'dw_pcie_setup_rc':
>> drivers/pci/controller/dwc/pcie-designware-host.c:746:22: warning: format '%llx' expects argument of type 'long long unsigned int', but argument 6 has type 'phys_addr_t {aka unsigned int}' [-Wformat=]
dev_dbg(pci->dev, "iATU: MEM window %d: base = %llx, bus_addr = %llx, size = %llx\n",
^
include/linux/dynamic_debug.h:135:39: note: in definition of macro 'dynamic_dev_dbg'
__dynamic_dev_dbg(&descriptor, dev, fmt, \
^~~
>> include/linux/device.h:1428:23: note: in expansion of macro 'dev_fmt'
dynamic_dev_dbg(dev, dev_fmt(fmt), ##__VA_ARGS__)
^~~~~~~
>> drivers/pci/controller/dwc/pcie-designware-host.c:746:4: note: in expansion of macro 'dev_dbg'
dev_dbg(pci->dev, "iATU: MEM window %d: base = %llx, bus_addr = %llx, size = %llx\n",
^~~~~~~
--
In file included from include/linux/printk.h:336:0,
from include/linux/kernel.h:14,
from include/linux/list.h:9,
from include/linux/preempt.h:11,
from include/linux/spinlock.h:51,
from include/linux/irq.h:14,
from include/linux/irqchip/chained_irq.h:21,
from drivers/pci//controller/dwc/pcie-designware-host.c:11:
drivers/pci//controller/dwc/pcie-designware-host.c: In function 'dw_pcie_setup_rc':
drivers/pci//controller/dwc/pcie-designware-host.c:746:22: warning: format '%llx' expects argument of type 'long long unsigned int', but argument 6 has type 'phys_addr_t {aka unsigned int}' [-Wformat=]
dev_dbg(pci->dev, "iATU: MEM window %d: base = %llx, bus_addr = %llx, size = %llx\n",
^
include/linux/dynamic_debug.h:135:39: note: in definition of macro 'dynamic_dev_dbg'
__dynamic_dev_dbg(&descriptor, dev, fmt, \
^~~
>> include/linux/device.h:1428:23: note: in expansion of macro 'dev_fmt'
dynamic_dev_dbg(dev, dev_fmt(fmt), ##__VA_ARGS__)
^~~~~~~
drivers/pci//controller/dwc/pcie-designware-host.c:746:4: note: in expansion of macro 'dev_dbg'
dev_dbg(pci->dev, "iATU: MEM window %d: base = %llx, bus_addr = %llx, size = %llx\n",
^~~~~~~
vim +746 drivers/pci/controller/dwc/pcie-designware-host.c
680
681 void dw_pcie_setup_rc(struct pcie_port *pp)
682 {
683 u32 val, ctrl, num_ctrls;
684 u64 remain_size, base, win_size;
685 phys_addr_t bus_addr;
686 int i;
687 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
688
689 dw_pcie_setup(pci);
690
691 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
692
693 /* Initialize IRQ Status array */
694 for (ctrl = 0; ctrl < num_ctrls; ctrl++)
695 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE +
696 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
697 4, &pp->irq_status[ctrl]);
698
699 /* Setup RC BARs */
700 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);
701 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
702
703 /* Setup interrupt pins */
704 dw_pcie_dbi_ro_wr_en(pci);
705 val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
706 val &= 0xffff00ff;
707 val |= 0x00000100;
708 dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
709 dw_pcie_dbi_ro_wr_dis(pci);
710
711 /* Setup bus numbers */
712 val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
713 val &= 0xff000000;
714 val |= 0x00ff0100;
715 dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val);
716
717 /* Setup command register */
718 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
719 val &= 0xffff0000;
720 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
721 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
722 dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
723
724 /*
725 * If the platform provides ->rd_other_conf, it means the platform
726 * uses its own address translation component rather than ATU, so
727 * we should not program the ATU here.
728 */
729 if (!pp->ops->rd_other_conf) {
730 /* Get iATU unroll support */
731 pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci);
732 dev_dbg(pci->dev, "iATU unroll: %s\n",
733 pci->iatu_unroll_enabled ? "enabled" : "disabled");
734
735 remain_size = pp->mem_size;
736 base = pp->mem_base;
737 bus_addr = pp->mem_bus_addr;
738
739 for (i = 0; remain_size > 0 && i < pp->mem_wins; i++) {
740 /*
741 * The maximum region size is 4 GB, and a region
742 * must not cross a 4 GB boundary.
743 */
744 win_size = SZ_4G - (base & (SZ_4G - 1));
745 win_size = min(win_size, remain_size);
> 746 dev_dbg(pci->dev, "iATU: MEM window %d: base = %llx, bus_addr = %llx, size = %llx\n",
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
Download attachment ".config.gz" of type "application/gzip" (30332 bytes)
Powered by blists - more mailing lists