linux-kernel - Re: [PATCH v9 6/9] i3c: master: Add driver for Cadence IP

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Message-ID: <20181025183005.3c0fa452@bbrezillon>
Date:   Thu, 25 Oct 2018 18:30:05 +0200
From:   Boris Brezillon <boris.brezillon@...tlin.com>
To:     Arnd Bergmann <arnd@...db.de>
Cc:     Wolfram Sang <wsa@...-dreams.de>,
        Linux I2C <linux-i2c@...r.kernel.org>,
        Jonathan Corbet <corbet@....net>,
        "open list:DOCUMENTATION" <linux-doc@...r.kernel.org>,
        gregkh <gregkh@...uxfoundation.org>,
        Przemyslaw Sroka <psroka@...ence.com>,
        Arkadiusz Golec <agolec@...ence.com>,
        Alan Douglas <adouglas@...ence.com>,
        Bartosz Folta <bfolta@...ence.com>,
        Damian Kos <dkos@...ence.com>,
        Alicja Jurasik-Urbaniak <alicja@...ence.com>,
        Cyprian Wronka <cwronka@...ence.com>,
        Suresh Punnoose <sureshp@...ence.com>,
        Rafal Ciepiela <rafalc@...ence.com>,
        Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
        Nishanth Menon <nm@...com>, Rob Herring <robh+dt@...nel.org>,
        Pawel Moll <pawel.moll@....com>,
        Mark Rutland <mark.rutland@....com>,
        Ian Campbell <ijc+devicetree@...lion.org.uk>,
        Kumar Gala <galak@...eaurora.org>,
        DTML <devicetree@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Vitor Soares <Vitor.Soares@...opsys.com>,
        Geert Uytterhoeven <geert@...ux-m68k.org>,
        Linus Walleij <linus.walleij@...aro.org>,
        Xiang Lin <Xiang.Lin@...aptics.com>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        Sekhar Nori <nsekhar@...com>,
        Przemyslaw Gaj <pgaj@...ence.com>,
        Peter Rosin <peda@...ntia.se>,
        Mike Shettel <mshettel@...eaurora.org>,
        Stephen Boyd <swboyd@...omium.org>,
        Joe Perches <joe@...ches.com>
Subject: Re: [PATCH v9 6/9] i3c: master: Add driver for Cadence IP

On Thu, 25 Oct 2018 18:13:51 +0200
Arnd Bergmann <arnd@...db.de> wrote:

> On Thu, Oct 25, 2018 at 6:07 PM Boris Brezillon
> <boris.brezillon@...tlin.com> wrote:
> >
> > On Thu, 25 Oct 2018 17:30:26 +0200
> > Arnd Bergmann <arnd@...db.de> wrote:
> >  
> > > On 10/24/18, Boris Brezillon <boris.brezillon@...tlin.com> wrote:  
> > > > Hi Arnd,
> > > >
> > > > On Mon, 22 Oct 2018 15:34:01 +0200
> > > > Boris Brezillon <boris.brezillon@...tlin.com> wrote:
> > > >
> > > >  
> > > >> +
> > > >> +static void cdns_i3c_master_rd_from_rx_fifo(struct cdns_i3c_master
> > > >> *master,
> > > >> +                                      u8 *bytes, int nbytes)
> > > >> +{
> > > >> +  readsl(master->regs + RX_FIFO, bytes, nbytes / 4);  
> > > >
> > > > Vitor reported a problem with readsl(): this function expects the 2nd
> > > > argument to be aligned on 32-bit, which is not guaranteed here. Unless
> > > > you see a better solution, I'll switch back to a loop doing:
> > > >
> > > >     for (i = 0; i < nbytes; i += 4) {
> > > >             u32 tmp = __raw_readl(...);
> > > >             memcpy(bytes + i, &tmp,
> > > >                    nbytes - i  > 4 ? 4 : nbytes - i);
> > > >     }  
> > >
> > > Could we maybe mandate that the buffer itself must be aligned here?
> > > What would be a reason why we see an unaligned target buffer?  
> >
> > Well, the buffers we pass to i3c_send_ccc_cmd() are not necessarily
> > aligned because they're not dynamically allocated (allocated on the
> > stack) and are not naturally aligned on 32-bits (either because they
> > are smaller than 32bits or because the struct is declared __packed).
> >
> > I guess I could dynamically allocate the payload, but that requires
> > going over all users of i3c_send_ccc_cmd() to patch them.  
> 
> This reminds me that Wolfram mentioned in his ELC talk that the
> buffers on i3c should all be DMA capable to make life easier for
> i3c master drivers that want to implement DMA transfers.

And this is the case for all buffers passed to
i3c_device_do_priv_xfers() (and soon i3c_device_send_hdr_cmd()),
but I did not enforce that for the internal
i3c_master_send_ccc_cmd_locked() helper, maybe I should...
It was just convenient to place the object to be transmitted/received on
the stack.

> 
> If we have buffers here that are not aligned to cache lines
> (or even just 32 bit words), doesn't that also mean that the
> same buffers are not DMA capable either?

Yep, if it's not cache-line-aligned (and on the stack), it's not
DMA-able.