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Message-ID: <20181028173503.GA4358@archbook>
Date: Sun, 28 Oct 2018 10:35:03 -0700
From: Moritz Fischer <mdf@...nel.org>
To: Andreas Puhm <puhm@...gano.at>
Cc: "matthew.gerlach@...ux.intel.com" <matthew.gerlach@...ux.intel.com>,
Moritz Fischer <mdf@...nel.org>,
Anatolij Gustschin <agust@...x.de>,
Alan Tull <atull@...nel.org>,
"linux-fpga@...r.kernel.org" <linux-fpga@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] fpga: altera_cvp: restrict registration to CvP enabled
devices
Hi Andreas,
On Thu, Oct 25, 2018 at 08:44:06AM +0000, Andreas Puhm wrote:
> >My experience with cvp is with Arria10 and Stratix 10. The PCIe Hard IP
> >gets configured when the IOring gets configured at power on. The idea is
> >that the load of the IOring is very fast, much before the infamous 100ms
> >PCIe timeout for link training. When the Hard IP is configured, the
> >CVP_EN is set or cleared according to how it was configured. Yes, you
>
> So is it correct that the value of CVP_EN can be evaluated by the altera_cvp right in the first call of its probe function
> (as would be the case with my proposed patch).
>
> If it is, I will fix the remaining issues with the patch and submit it.
Yes please, go ahead and fix up the remaining issues (+ send it using
git send-email)
Thanks,
Moritz
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