linux-kernel - Re: [PATCH linux-next v1 2/4] clk: renesas: Add binding document for AVB Counter Clock

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <154083775062.98144.11157403961171783929@swboyd.mtv.corp.google.com>
Date:   Mon, 29 Oct 2018 11:29:10 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     geert+renesas@...der.be, horms@...ge.net.au, jiada_wang@...tor.com,
        magnus.damm@...il.com, mark.rutland@....com,
        mturquette@...libre.com, robh+dt@...nel.org
Cc:     linux-kernel@...r.kernel.org, linux-renesas-soc@...r.kernel.org,
        linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
        jiada_wang@...tor.com
Subject: Re: [PATCH linux-next v1 2/4] clk: renesas: Add binding document for AVB
 Counter Clock

Quoting jiada_wang@...tor.com (2018-10-25 00:23:47)
> From: Jiada Wang <jiada_wang@...tor.com>
> 
> Add device tree bindings for avb counter clock for Renesas
> R-Car Socs.
> 
> Signed-off-by: Jiada Wang <jiada_wang@...tor.com>
> ---
>  .../bindings/clock/renesas,avb-clk.txt        | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/renesas,avb-clk.txt
> 
> diff --git a/Documentation/devicetree/bindings/clock/renesas,avb-clk.txt b/Documentation/devicetree/bindings/clock/renesas,avb-clk.txt
> new file mode 100644
> index 000000000000..03bf50b5830c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/renesas,avb-clk.txt
> @@ -0,0 +1,19 @@
> +* Renesas AVB Counter Clock
> +
> +The AVB Counter Clocks are provided by avb_counter8 Clock Generator,
> +avb_counter8 has dividers which operates with S0D1ϕ clock and has
> +8 output clocks.
> +
> +Required Properties:
> +  - compatible: Must be "renesas,clk-avb"
> +  - reg: Base address and length of the memory resource used by the AVB
> +  - #clock-cells: Must be 1
> +
> +Example
> +-------
> +
> +       clk_avb: avb-clock@...a011c {
> +               compatible = "renesas,clk-avb";
> +               reg = <0 0xec5a011c 0 0x24>;

This is an odd register offset. Is this just one clk inside of a larger
clk controller?