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Message-ID: <CACRpkdYJW34oRmm0ZBivwsa7mMXhrj8hxz+ovXNwnOETs3xrog@mail.gmail.com>
Date: Wed, 31 Oct 2018 15:05:16 +0100
From: Linus Walleij <linus.walleij@...aro.org>
To: Jerome Brunet <jbrunet@...libre.com>
Cc: Kevin Hilman <khilman@...libre.com>,
Carlo Caione <carlo@...one.org>,
Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
"open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
"open list:ARM/Amlogic Meson..." <linux-amlogic@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 0/4] pinctrl: meson: fix pull bits
On Mon, Oct 29, 2018 at 4:13 PM Jerome Brunet <jbrunet@...libre.com> wrote:
> This patchset fixes the inversion between pull (up/down) and pull enable
> bits on the GPIO AO bank of all amlogic when have, except the axg family.
>
> The problem has been found while testing bias setting on the libretech
> aml-s905x-cc on GPIO_AO 5. Unfortunately the bias register of this bank is
> not described in the public datasheet of the s905x, but it is in the
> one of the A113D, which gave a clue.
>
> This was tested on gxl libretech aml-s905x-cc. Since all Amlogic we have
> got so far derive from each other, there is no reason for things to be
> any different on the meson8(b).
>
> I would have preferred to make a single patch to fix this but the commit
> introducing the mistake the is different for each SoC, so a single patch
> could be more difficult/annoying to backport.
All patches applied for fixes.
Thanks for drilling into this!
Yours,
Linus Walleij
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